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Design of Booth Multiplier using Double Gate MOSFET

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Yogeesh K.V., Venkateshkumar H.
10.5120/ijca2017914241

Yogeesh K.V. and Venkateshkumar H.. Design of Booth Multiplier using Double Gate MOSFET. International Journal of Computer Applications 167(4):19-23, June 2017. BibTeX

@article{10.5120/ijca2017914241,
	author = {Yogeesh K.V. and Venkateshkumar H.},
	title = {Design of Booth Multiplier using Double Gate MOSFET},
	journal = {International Journal of Computer Applications},
	issue_date = {June 2017},
	volume = {167},
	number = {4},
	month = {Jun},
	year = {2017},
	issn = {0975-8887},
	pages = {19-23},
	numpages = {5},
	url = {http://www.ijcaonline.org/archives/volume167/number4/27760-2017914241},
	doi = {10.5120/ijca2017914241},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Double gate MOSFET technology is used wherever low power delay product is desired. It uses to reduce leakage current drain induced barrier lowering effect (DIBL) and other short channel affects. In this work 8×8, Booth Multiplier is analysed in 90nm technology, with one single-gate MOSFET technology and then other using the proposed that is Double-Gate MOSFET technique. Depending on the input patterns, the proposed technique saves 24% in power consumption has observed in proposed circuit. Design and simulations are performed in cadence virtuoso and spectre tools using 90nm technology.

References

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Keywords

Booth Multiplier, Double Gate, Low power, Power Delay Product (PDP)