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Design and Synthesis of High Performance Vedic DSP Processor

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Anuradha Savadi, Raju Yanamshetti, Jyoti Godihal

Anuradha Savadi, Raju Yanamshetti and Jyoti Godihal. Design and Synthesis of High Performance Vedic DSP Processor. International Journal of Computer Applications 168(6):27-32, June 2017. BibTeX

	author = {Anuradha Savadi and Raju Yanamshetti and Jyoti Godihal},
	title = {Design and Synthesis of High Performance Vedic DSP Processor},
	journal = {International Journal of Computer Applications},
	issue_date = {June 2017},
	volume = {168},
	number = {6},
	month = {Jun},
	year = {2017},
	issn = {0975-8887},
	pages = {27-32},
	numpages = {6},
	url = {},
	doi = {10.5120/ijca2017914469},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


To satisfy the prerequisite of rapid speed signal processing design of high performance DSP processor is renowned. This paper represents a novel design and FPGA based pursuit of 64 bit DSP processor. The proposed design implicates multistage pipeline architecture and vedic algorithms to improve the speed. The DSP processor is rich with multiple application specific instructions (ASIP). The verilog HDL is used and the validated through extensive simulation. Synthesis results and attainment scrutiny of each systems components confirmed significant performance meliorism in the proffered DSP processor over the extant one..


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DSP Processor, Pipelining, Vedic mathematics, ASIP.