Call for Paper - July 2023 Edition
IJCA solicits original research papers for the July 2023 Edition. Last date of manuscript submission is June 20, 2023. Read More

FTL based 4Stage CLA Adder Design with Floating Gates

International Journal of Computer Applications
© 2011 by IJCA Journal
Number 6 - Article 1
Year of Publication: 2011
M.Murali Krishna
Malleswara Rao.V

P.H.S.T.Murthy, K.Chaitanya, M.Murali Krishna and Malleswara Rao.V. Article: FTL based 4Stage CLA Adder Design with Floating Gates. International Journal of Computer Applications 17(6):1-5, March 2011. Full text available. BibTeX

	author = {P.H.S.T.Murthy and K.Chaitanya and M.Murali Krishna and Malleswara Rao.V},
	title = {Article: FTL based 4Stage CLA Adder Design with Floating Gates},
	journal = {International Journal of Computer Applications},
	year = {2011},
	volume = {17},
	number = {6},
	pages = {1-5},
	month = {March},
	note = {Full text available}


Low-voltage and low-power circuit structures are substantive for almost all mobile electronic gadgets which generally have mixed mode circuit structures embedded with analog sub-sections. Using the reconfigurable logic of multi-input floating gate MOSFETs, 4-bit full adder has been designed for 1.1V operation. [1],[2] Multi-input floating gate (MIFG) transistors have been anticipating in realizing the increased functionality on a chip. A multi-input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. Implementing a design using multi-input floating gate MOSFETs brings down transistor count and number of interconnections. Here in this we have presented how to eliminate the propagate and generate signals this tends the design to become more efficient in area and power consumption by using feed through logic [8]. It has been included the four stage sum signal in FTL based adder with floating gates. The following information is about Carry look ahead adder circuit, tested with 45nm technology and is extended to ALU. The proposed circuit has been implemented in 45n-well CMOS technology.


  • Modeling multiple-input floating-gate transistors for analog signal processing, 1997 IEEE International Symposium on Circuits and Systems, June 9-1-2, 1997, Hong Kong
  • Y. Tsividis, Operation and Modeling of the MOS Transistor, Mc Graw-Hill, 1999.
  • J.M. Rabaey, Digital Integrated Circuits- A Design Perspective, Prentice Hall, 1996.
  • V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi
  • Bardia Bozorgzadeh1, Ehsan Zhian-Tabasy1, and Ali Afzali-Kusha1,2008 IEEEInternational Conference on Microelectronics“Analysis of high-performance fast Feedthrough Logic families”
  • CMOS Digital Integrated circuits Analysis and Design by Sung-Mo Kang and Yusuf Leblebici
  • Mangith borah ,Robert Michel owens “Transistor sizing in low power CMOS circuits”, IEEE Transactions on computer aided design integrated circuits and systems, volume 15, No.6, June 1996.
  • CMOS Logic circuit Design by John P. uyemura