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Design and Evaluation of FinFET based SRAM Cells at 22nm and 14nm Node Technologies

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Raju Hajare, C. Lakhminarayana
10.5120/ijca2017915005

Raju Hajare and C Lakhminarayana. Design and Evaluation of FinFET based SRAM Cells at 22nm and 14nm Node Technologies. International Journal of Computer Applications 171(6):26-31, August 2017. BibTeX

@article{10.5120/ijca2017915005,
	author = {Raju Hajare and C. Lakhminarayana},
	title = {Design and Evaluation of FinFET based SRAM Cells at 22nm and 14nm Node Technologies},
	journal = {International Journal of Computer Applications},
	issue_date = {August 2017},
	volume = {171},
	number = {6},
	month = {Aug},
	year = {2017},
	issn = {0975-8887},
	pages = {26-31},
	numpages = {6},
	url = {http://www.ijcaonline.org/archives/volume171/number6/28186-2017915005},
	doi = {10.5120/ijca2017915005},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In today’s world scenario more than 85-90% of the chip area is mainly occupied by memory. There is a need for faster and reliable memory system for various integrated devices from computers to various handheld devices. The memory devices such as SRAM, DRAM etc. were served by the traditional MOSFETs till to date but as the demand of the better performing and the compact modeling of the integrated devices are causing the failure of MOSFETs operations. The MOSFET scaling is suffered by Short Channel Effects (SCE’s). SRAM is one of the memories mainly used in the cache memory of devices. It must be faster, less power consuming and reliable but this is affected by CMOS scaling causing process variations. Here in this paper the alternate solution to the issues faced by MOSFET based SRAM is overcome by FinFET based SRAM. A 6T short gated FinFET based SRAM is taken for the study and the spice models are created at 22nm and 14nm using Predictive Technology Models (PTM) and simulated using HSPICE. The performance is analyzed in terms of Static Noise Margin (SNM), power and delay for the 6T SRAM. The results shows FinFET based SRAM is faster, reliable and the power consumption is significantly reduced and offers good trade-offs at lower technology nodes.

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Keywords

SRAM Cell, FinFET, CMOS, SNM, PTM Read delay, Write delay