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Design and Implementation of Lempel-Ziv Data Compression using FPGA

by Gehad Mohey, Abdelhalim Zekry, Hatem Zakaria
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 174 - Number 12
Year of Publication: 2021
Authors: Gehad Mohey, Abdelhalim Zekry, Hatem Zakaria
10.5120/ijca2021921008

Gehad Mohey, Abdelhalim Zekry, Hatem Zakaria . Design and Implementation of Lempel-Ziv Data Compression using FPGA. International Journal of Computer Applications. 174, 12 ( Jan 2021), 38-45. DOI=10.5120/ijca2021921008

@article{ 10.5120/ijca2021921008,
author = { Gehad Mohey, Abdelhalim Zekry, Hatem Zakaria },
title = { Design and Implementation of Lempel-Ziv Data Compression using FPGA },
journal = { International Journal of Computer Applications },
issue_date = { Jan 2021 },
volume = { 174 },
number = { 12 },
month = { Jan },
year = { 2021 },
issn = { 0975-8887 },
pages = { 38-45 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume174/number12/31734-2021921008/ },
doi = { 10.5120/ijca2021921008 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:21:57.011447+05:30
%A Gehad Mohey
%A Abdelhalim Zekry
%A Hatem Zakaria
%T Design and Implementation of Lempel-Ziv Data Compression using FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 174
%N 12
%P 38-45
%D 2021
%I Foundation of Computer Science (FCS), NY, USA
Abstract

When transmitting the data in digital communication, it is well desired that the transmitting data bits should be as minimal as possible, so many techniques are used to compress the data. In this paper, a Lempel-Ziv algorithm for data compression was implemented through VHDL coding. The Lempel-Ziv algorithm is one of the most widely used among lossless data compression algorithms for hardware implementation. The work in this paper is devoted to improve the compression rate, space-saving, and utilization of the Lempel-Ziv algorithm using a systolic array approach. The developed design is validated with VHDL simulations using Xilinx ISE 14.5 and synthesized on Virtex-6 FPGA chip. The results show that our design is efficient in providing high compression rates as well as improved utilization. The Throughput is increased by 50% and the design area is decreased by more than 23% with a high compression ratio compared to comparable previous designs. (

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Index Terms

Computer Science
Information Sciences

Keywords

Data Compression Lossless compression VHDL FPGA Design Utilization CODEC LZSS LZ77 Systolic array design