CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Universal Set of Reversible Quaternary Logic Gates

by Milton Ernesto Romero Romero, Diogo Anache De Souza, Evandro Mazina Martins
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 174 - Number 27
Year of Publication: 2021
Authors: Milton Ernesto Romero Romero, Diogo Anache De Souza, Evandro Mazina Martins
10.5120/ijca2021921199

Milton Ernesto Romero Romero, Diogo Anache De Souza, Evandro Mazina Martins . Universal Set of Reversible Quaternary Logic Gates. International Journal of Computer Applications. 174, 27 ( Mar 2021), 29-36. DOI=10.5120/ijca2021921199

@article{ 10.5120/ijca2021921199,
author = { Milton Ernesto Romero Romero, Diogo Anache De Souza, Evandro Mazina Martins },
title = { Universal Set of Reversible Quaternary Logic Gates },
journal = { International Journal of Computer Applications },
issue_date = { Mar 2021 },
volume = { 174 },
number = { 27 },
month = { Mar },
year = { 2021 },
issn = { 0975-8887 },
pages = { 29-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume174/number27/31846-2021921199/ },
doi = { 10.5120/ijca2021921199 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:23:15.337808+05:30
%A Milton Ernesto Romero Romero
%A Diogo Anache De Souza
%A Evandro Mazina Martins
%T Universal Set of Reversible Quaternary Logic Gates
%J International Journal of Computer Applications
%@ 0975-8887
%V 174
%N 27
%P 29-36
%D 2021
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reversible computing is of great interest due to the fact that the next generation of high performance computers must decrease heat dissipation in order to be practical, and irreversible gates dissipate energy into the environment because of the loss of information. This paper takes advantage of Multiple Valued Logic (MVL) quaternary universal set, that reduces integrated circuits (IC) interconnections, decreasing IC area, and with reversible gates that minimizes IC dissipation. The reversible computation permits both forward and backward computations, keeping the information entropy constant and decreasing heat dissipation, according to Landauer principle. The reversible gates are designed as an extension of the set of gates: Extended AND (eANDi: eAND1, eAND2, eAND3), Maximum (MAX) and Successor (SUC) already proposed in the literature. The voltage mode gates are implemented by means of three cascaded subsystems: the first subsystem discriminates 0,1,2,3 logical levels; the second subsystem performs the logic to implement each operator functionality; and the third subsystem set the right voltage output corresponding to 0,1,2,3 logical levels. Simulations with only 25, 18, 32, 10 and 32 CMOS transistors, respectively, utilizing AustriamicrosystemsTM technology with Cadence VirtuosoTM tool demonstrate correct circuit behavior. These implementations present, for the irreversible circuits presented in the literature, fewer number of transistors.

References
  1. Feynman, R. P.: “Quantum mechanical computers”, Foundations of Physics, 1986, 16, (6), pp. 507-531.
  2. Biswas, P. K., Bahar, A. N., Habib, M. A., et al.: “Efficient design of Feynman and Toffoli gate in quantum dot cellular automata (QCA) with Energy Dissipation Analysis”, Nanoscience and Nanotechnology, 2017, 7, (2), pp. 27-33.
  3. Picton, P.: “Multi-valued sequential logic design using Fredkin gates”, Multiple-Valued Logic Journal, 1996, 1, (4), pp. 241- 251.
  4. Thapliyal, H., Srinivas, M. B., Zwolisnki, M.: “A beginning in the reversible logic synthesis of sequential circuits”. Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD), 2005, 4, pp. 6-9.
  5. Thapliyal, H., Ranganathan, N.: “Reversible logic based concurrent error detection methodology for emerging nanocircuits”. 10th IEEE International Conference on Nanotechnology, Seoul, South Korea, August 2010, pp. 217-222.
  6. Morrison, M., Ranganathan, N.: “Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up counter”. 11th IEEE International Conference on Nanotechnology, Portland, USA, August 2011, pp. 1445- 1449.
  7. Taylor, M. B.: “Is dark silicon useful? harnessing the four horsemen of the coming dark silicon apocalypse”. Design Automation Conference (DAC), San Francisco, USA, June 2012, pp. 1131-1136.
  8. Toffoli, T.: “Reversible computing”. International Colloquium on Automata, Languages, and Programming, Berlin, Heidelberg, Germany, July 1980, pp. 632-644.
  9. Bennett, C. H.: “Logical reversibility of computation”, IBM journal of Research and Development, 1973, 17, (6), pp. 525- 532.
  10. Rangaraju H. G., Aakash S. Muralidhara N.: (2012). “Design and Optimization of Reversible Multiplier Circuit”, International Journal of Computer Applications, 2012, (52), pp. 44-50.
  11. Singh V., Gupta R.: “A Novel n-bit Arithmetic Logic Unit Design based on Reversible Logic”. IJCA Proceedings on National Symposium on Modern Information and Communication Technologies for Digital India MICTDI, 2016, pp. 27- 30.
  12. A. Sadat Md. Sayem and Ueda M.: “Optimization of Reversible Sequential Circuits”, Journal of Computing, 2010, 2, (6), pp.208-214.
  13. Hari, S. K. S., Shroff, S., Mahammad, S. N., et al.: “Efficient building blocks for reversible sequential circuit design”. 2006 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico, August 2006, pp. 437-441.
  14. Taha, S. M. R.: “Reversible logic synthesis methodologies with application to quantum computing” (Springer International Publishing, 1st edn. 2016).
  15. Athas, W. C., Svensson, L. J.: “Reversible logic issues in adiabatic CMOS”. Proceedings Workshop on Physics and Computation. PhysComp’94, Dallas, USA, November 1994, pp. 111-118.
  16. Maslov, D., Dueck, G.W.: “Reversible cascades with minimal garbage”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23, (11), pp. 1497- 1509.
  17. Gupta, Y. and Sasamal, T. N.: “Implementation of reversible logic gates using adiabatic logic”. 2015 IEEE Power, Communication and Information Technology Conference (PCITC), Bhubaneswar, India, October 2005, pp. 595-598.
  18. Schaeffer, B., Tran, L., Gronquist, A., et al.: “Synthesis of Reversible Circuits Based on Products of Exclusive OR Sums”. 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, Toyama, Japan, May 2013, pp. 35-40.
  19. Singla, P., Prasad, R. R.: “Transistor Implementation Of Reversible Gate Using Novel 3 Transistor EX-OR Gate”. Global Journal of Advanced Research, Jan. 2015, 2, (1), pp. 46-49.
  20. Raj, K. P., Syamala, Y.: “Transistor level implementation of digital reversible circuits”, International Journal of VLSI Design & Communication Systems, 2014, 5, (6), pp. 43.
  21. Majumdar, R., Saini, S.: “A novel design of reversible 2:4 decoder”. 2015 International Conference on Signal Processing and Communication (ICSC), Noida, India, March 2015, pp. 324-327.
  22. Bhardwaj, R.: “Reversible logic gates and its performances”. 2018 2nd International Conference on Inventive Systems and Control (ICISC), Coimbatore, India, January 2018, pp. 226- 231.
  23. Kerntopf, P., Perkowski, M., Podlaski, K.: “Synthesis of reversible circuits: A view on the state-of-the-art”. 2012 12th IEEE International Conference on Nanotechnology (IEEENANO), Birmingham, UK, August 2012, pp. 1-6.
  24. Post, E. L.: “Introduction to a general theory of elementary propositions”, American Journal of Mathematics, 1920, 43, (3), pp. 163-185.
  25. Lukasiewicz J.: “On three valued-logic.”, eds. L. Borkowski (Select Works, North-Holland, Amsterdam), 1920, pp. 169- 171.
  26. Hurst, S. L.: “Multiple-valued logic its status and its future”, IEEE transactions on Computers, 1984, (12), pp. 1160-1179.
  27. Smith, K.: “A multiple valued logic: a tutorial and appreciation”, Computer, 1988, 21, (4), pp. 17-27.
  28. KS, V. P., Gurumurthy K. S.: “Quaternary CMOS combinational logic circuits”. 2009 International Conference on Information and Multimedia Technology, Jeju Islan, South Korea, December 2009, pp. 538-542.
  29. Romero, M. E. R., Martins, E. M., Santos, R. R.: “Multiple valued logic algebra for the synthesis of digital circuits”. 2009 39th International Symposium on Multiple-Valued Logic, Naha, Japan, May 2009, pp. 262-267.
  30. Romero, M. E. R., Martins, E. M., Santos, R. R., Duarte, G. M.: “Universal set of CMOS gates for the synthesis of multiple valued logic digital circuits”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2013, 61, (3), pp. 736-749.
  31. Romero, M. E. R., Martins, E. M., Santos, R. R., Duarte, G. M.: “Analog to digital converter for binary and multiple-valued logic”. 2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), Bogota, Colombia, February 2011, pp. 1-4.
  32. Madhuri, B. D., Sunithamani, S.: “Design of ternary logic gates and circuits using GNRFETs”, IET Circuits, Devices & Systems, 2020, 14, (7), pp. 972-979.
  33. Landauer, R.: “Irreversibility and heat generation in the computing process”, IBM J. Research and Development, 1961, 5, (3), pp. 183-191.
Index Terms

Computer Science
Information Sciences

Keywords

Reversible Computing Universal Quaternary Set Multiple Valued Logic

Powered by PhDFocusTM