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Reseach Article

FPGA Design and Implementation for Huge Data Manipulation Systems

by Asmaa Hameed Rasheed
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 174 - Number 7
Year of Publication: 2017
Authors: Asmaa Hameed Rasheed
10.5120/ijca2017915428

Asmaa Hameed Rasheed . FPGA Design and Implementation for Huge Data Manipulation Systems. International Journal of Computer Applications. 174, 7 ( Sep 2017), 18-23. DOI=10.5120/ijca2017915428

@article{ 10.5120/ijca2017915428,
author = { Asmaa Hameed Rasheed },
title = { FPGA Design and Implementation for Huge Data Manipulation Systems },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2017 },
volume = { 174 },
number = { 7 },
month = { Sep },
year = { 2017 },
issn = { 0975-8887 },
pages = { 18-23 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume174/number7/28419-2017915428/ },
doi = { 10.5120/ijca2017915428 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:21:30.941136+05:30
%A Asmaa Hameed Rasheed
%T FPGA Design and Implementation for Huge Data Manipulation Systems
%J International Journal of Computer Applications
%@ 0975-8887
%V 174
%N 7
%P 18-23
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The FPGAs will continue to be used for many of today’s digital signal processing applications. The reasons for this are firstly FPGAs are highly configurable hardware, since it has a grid of reconfigurable gate structure. The second reason is MIPS and MMACS (Millions of instructions and Millions of Multiply-Accumulate Operations executed per Second) requirements of specific application. Although FPGAs have their limitations and processing restrictions. The main obstacle of using FPGA with huge data processing systems is the limited number of pins of the FPGA kit that restrict the number of input samples that must be processed simultaneously. This paper describes an efficient FPGA based hardware design with the assistance of XSG (Xilinx System Generator) applied for huge data systems. The used approach is a windowing technique to cut specified number of pixels from a huge data using Xilinx System Generator block sets to build the required digital system design that can be converted to a hardware co-simulation design which is defined for FPGA environments . Image filtering techniques and algorithms are used in this work for testing the proposed approach. Xilinx software ISE 14.7 with (VHDL) language for Spartan3-700A and MATLAB R2013a are the combined S/W for hardware co-simulation design.

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Index Terms

Computer Science
Information Sciences

Keywords

FPGA Xilinx system generator (XSG) Data processing image processing.