CFP last date
22 April 2024
Reseach Article

Design of Nova Decoder for H.265/HEVC

by Anuradha Savadi, Raju Yanamshetti, Sherqua Asma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 179 - Number 11
Year of Publication: 2018
Authors: Anuradha Savadi, Raju Yanamshetti, Sherqua Asma
10.5120/ijca2018916122

Anuradha Savadi, Raju Yanamshetti, Sherqua Asma . Design of Nova Decoder for H.265/HEVC. International Journal of Computer Applications. 179, 11 ( Jan 2018), 35-40. DOI=10.5120/ijca2018916122

@article{ 10.5120/ijca2018916122,
author = { Anuradha Savadi, Raju Yanamshetti, Sherqua Asma },
title = { Design of Nova Decoder for H.265/HEVC },
journal = { International Journal of Computer Applications },
issue_date = { Jan 2018 },
volume = { 179 },
number = { 11 },
month = { Jan },
year = { 2018 },
issn = { 0975-8887 },
pages = { 35-40 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume179/number11/28847-2018916122/ },
doi = { 10.5120/ijca2018916122 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:55:06.060394+05:30
%A Anuradha Savadi
%A Raju Yanamshetti
%A Sherqua Asma
%T Design of Nova Decoder for H.265/HEVC
%J International Journal of Computer Applications
%@ 0975-8887
%V 179
%N 11
%P 35-40
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper represents the Nova decoder design for latest standard of video coding H.265/HEVC. Power optimization is the main priority of the propound decoder at various levels of the system like wise physical, circuit, algorithm and architecture levels. The proposed design is able to decode QCIF 30fps at maximum frequency with optimized power supply and 80% in area reduction with UMC 180nm technology. Video quality and less power dissipation is the highest priority for the portable devices in the present era in which our propound design will meet all requirements.

References
  1. ke xu chiu sing choy “low power h.264/avc baseline decoder for portable applications” ,ISLPED 07,august 27-29,2007, Portland,Oregon,USA copyright 2007 ACM 978-1-59593-709-4/07/008.
  2. ke xu chiu sing choy “Priority-Based heading one detector in H.264/AVC decoding”, EURASIP journal on Embedded System, vol. 2007, Article ID 60834. 2007
  3. Waleed Ahmed EI- ghobashy, Mohammed Ebian, et. al “An efficient implementation method of H.264 CAVLC video coding using FPGA”, DOI 978-1-5090-0275-7/15, pp.212-216, IEEE conference 2015.
  4. Maleen abeydeera, Manupa Karunaratne et.al “4K Real time HEVC Decoder on FPGA”, IEEE transactions on Circiuts and systems for video technology, TCSVT 2015.
  5. Gary j.sullivan “overview of high efficiency video coding (HEVC)standard.1051-8215 2012 IEEE.
  6. Seongmo Park, Hanjin Cho, Heebum Jung , and Dukdong Lee, “An Implemented of H.264 Video Decoder using Hardware and Software” analyzed implementation.
  7. D.wu,w.Gao,M.Z.Hu,Z.Z.Ji,”A VLSI architecture design of CAVLC decoder”,The 5th international conference on ASIC,oct.2003,pp.962-965.
  8. k.xu,C.S.choy, C.F. chan,K.P.pun,”A low power bitstream controller for H.264/AVC baseline decoding”,32ND European solid stste circuits conference,pp.162-165, sep 2006.
  9. Tsu-Ming Liu, Wen-Ping Lee, Ting-An Lin and Chen-Yi Lee “A Memory-efficient Deblocking filter for h.264/avc video coding” by the National Science Council of Taiwan, R.O.C., under Grant NSC 93-2220-E-009 -010.
  10. Hae-Yong Kang, Kyung-Ah Jeong, Jung-Yang Bae, Young-Su Lee, Seung-Ho Lee “MPEG4 avc/h.264 decoder with scalable bus architecture and dual memory controller”.0-7803-8251-X/04/$17.00 2004 IEEE.
  11. Tung-Chien Chen, Chung-Jr Lian, and Liang-Gee Chen “Hardware Architecture Design of an H.264/AVC Video Codec”. 0-7803-9451-8/06/$20.00 2006 IEEE
Index Terms

Computer Science
Information Sciences

Keywords

H.265/HEVC Baseline Decoder CAVLC / CABAC.