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Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

by Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 179 - Number 23
Year of Publication: 2018
Authors: Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami
10.5120/ijca2018916476

Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami . Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits. International Journal of Computer Applications. 179, 23 ( Feb 2018), 39-43. DOI=10.5120/ijca2018916476

@article{ 10.5120/ijca2018916476,
author = { Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami },
title = { Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits },
journal = { International Journal of Computer Applications },
issue_date = { Feb 2018 },
volume = { 179 },
number = { 23 },
month = { Feb },
year = { 2018 },
issn = { 0975-8887 },
pages = { 39-43 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume179/number23/29011-2018916476/ },
doi = { 10.5120/ijca2018916476 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:56:16.007955+05:30
%A Adel Alimoradi
%A Pourya Rostami Gooran
%A Manoocheher Karami
%T Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 179
%N 23
%P 39-43
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a novel approach at circuit level named LSP is proposed by combination of LECTOR, Stack and Pass transistors techniques to decrease leakage power dissipation during active and standby mode. As a result, pass transistors are utilized to maintain logic state of network in the standby mode. Proposed technique simulation has been performed using HSPICE software in 32 nanometer technology with supply voltage 0.6V. According to achieved results by NAND gate and full adder circuits, sub-threshold current is decreased by 80% in compared to base case, 70% to LECTOR and 20% to Sleepy Keeper.

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Index Terms

Computer Science
Information Sciences

Keywords

Leakage power LECTOR technique Low power Stack technique VLSI.

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