Call for Paper - April 2020 Edition
IJCA solicits original research papers for the April 2020 Edition. Last date of manuscript submission is March 20, 2020. Read More

A New Efficient Residue to Binary Converter for (5n+2)-bit Dynamic Range Moduli Set

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2018
Salifu Abdul-Mumin, Mohammed Ibrahim Daabo, Akobre Stephen

Salifu Abdul-Mumin, Mohammed Ibrahim Daabo and Akobre Stephen. A New Efficient Residue to Binary Converter for (5n+2)-bit Dynamic Range Moduli Set. International Journal of Computer Applications 179(34):18-21, April 2018. BibTeX

	author = {Salifu Abdul-Mumin and Mohammed Ibrahim Daabo and Akobre Stephen},
	title = {A New Efficient Residue to Binary Converter for (5n+2)-bit Dynamic Range Moduli Set},
	journal = {International Journal of Computer Applications},
	issue_date = {April 2018},
	volume = {179},
	number = {34},
	month = {Apr},
	year = {2018},
	issn = {0975-8887},
	pages = {18-21},
	numpages = {4},
	url = {},
	doi = {10.5120/ijca2018916726},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


This paper proposes an efficient residue to binary converter on a new three-moduli set (2(2n+1),2(2n+1)-1,2n-1) using the Mixed Radix Conversion. The proposed reverse converters are adder based and memoryless. In comparison with other moduli sets with similar dynamic range, the new schemes out-perform the existing schemes in terms of both hardware cost and propagation delay.


  1. N.S. Szabo and R.I. Tanaka, Residue arithmetic and its applications to computer technology, McGraw Hill, New York, 1967.
  2. M.A. Sonderstrand, W.K. Jenkins, G.A. Jullien, and F.J. Taylor, Residue number system arithmetic: Modern applications in digital signal processing, IEEE Press, New York, 1986.
  3. M. Bhardwaj, T. Srikanthan, and C. T. Clarke, “A reverse converter for the 4 moduli super set {2^n-1, 2^n, 2^n+1, 2^(n+1)+1},” IEEE Conf. Comput. Arith., 1999.
  4. A. Hariri, R. Rastegar, and K. Navi, “High Dyanamic Range 3-Moduli Set with Efficient Reverse Converter,” Int. J. Comput. Math. Appl.
  5. S. Abdul-Mumin, P. A. Agbedemnab and M. I. Daabo: New Efficient Reverse Converters for 8n-bit Dynamic Range Moduli Set, International Journal of Computer Applications Volume 161 – No 9, pp: 23-27March 2017
  6. E. K. Bankas and K. A. Gbolagade, “A New Efficient FPGA Design of Residue-To-Binary Converter,” Int. J. VLSI Des. Commun. Syst. VLSICS, vol. 4, no. 6, Dec. 2013.
  7. H. Pettenghi, R. Chaves, and L. Sousa, “RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to -bit,” IEEE Trans. Circuits Syst. Regul. Pap., vol. 60, no. 6, pp. 1487–1500, Jun. 2013.
  8. M. I. Daabo and K. A. Gbolagade, “RNS Overflow Detection Scheme for the Moduli set {M − 1, M},” J. Comput., vol. 4, no. 8, pp. 39–44, 2012.
  9. K. A. Gbolagade, “New Adder-Based RNS-Binary Converters for the {2^(n+1)+1,2^(n+1)-1,2^n } Moduli Set.,” Int. Sch. Res. Netw
  10. G. Jaberipur and H. Ahmadifar, “A ROM-less reverse RNS converter for moduli set 2q ?? 1, 2q ?? 3,” IET Comput. Digit. Tech., vol. 8, no. 1, pp. 11–22, Jan. 2014.
  11. Y. Wang, X. Song, M. Aboulhamid, and H. Shen, “Adder-based residue to binary number converters for (2n − 1, 2n, 2n + 1),” IEEE Trans. Signal Process., vol.50, no.7, pp.1772–1779, July 2002.
  12. W.Wang, M.N.S. Swamy, M.O. Ahmad, and Y.Wang, “A study of the residue-to-binary converters for the three-moduli sets,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.50, no.2, pp.235–245, Feb. 2003.
  13. B. Cao, C.H. Chang, and T. Srikanthan, “An efficient reverse converter for the 4-moduli set (2n − 1, 2n, 2n + 1, 22n + 1) based on the new Chinese remainder theorem,” IEEE Trans. Circuits Syst. I, vol.50, no.10, pp.1296–1303, Oct. 2003.
  14. B. Cao, T. Srikanthan, and C.H. Chang, “Efficient reverse converters for the four-moduli sets (2n − 1, 2n, 2n + 1, 2n+1 − 1) and (2n −1, 2n, 2n +1, 2n−1 −1),” Proc. IEE Comput. Digit. Tech., vol.152, no.5, pp.687–696, Sept. 2005.
  15. A.A. Hiasat, “VLSI implementation of new arithmetic residue to binary decoders,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.13, no.1, pp.153–158, Jan. 2005.
  16. P.V.A. Mohan, “RNS-to-binary converter for a new three-moduli set (2n+1 − 1, 2n, 2n − 1),” IEEE Trans. Circuits Syst. II, vol.54, no.9, pp.775–779, Sept. 2007.
  17. P. V. Ananda Mohan and A. B. Premkumar, “RNS-to-binary converters for two four-moduli sets {2


Reverse Converter, Mixed Radix Conversion, Dynamic Range, Moduli Set, Residue Number System