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Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System

by Yunxiang Zhang, Xiaokun Yang, Lei Wu, Archit Gajjar, Han He
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 180 - Number 17
Year of Publication: 2018
Authors: Yunxiang Zhang, Xiaokun Yang, Lei Wu, Archit Gajjar, Han He

Yunxiang Zhang, Xiaokun Yang, Lei Wu, Archit Gajjar, Han He . Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System. International Journal of Computer Applications. 180, 17 ( Feb 2018), 1-7. DOI=10.5120/ijca2018916380

@article{ 10.5120/ijca2018916380,
author = { Yunxiang Zhang, Xiaokun Yang, Lei Wu, Archit Gajjar, Han He },
title = { Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System },
journal = { International Journal of Computer Applications },
issue_date = { Feb 2018 },
volume = { 180 },
number = { 17 },
month = { Feb },
year = { 2018 },
issn = { 0975-8887 },
pages = { 1-7 },
numpages = {9},
url = { },
doi = { 10.5120/ijca2018916380 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-07T01:00:53.503481+05:30
%A Yunxiang Zhang
%A Xiaokun Yang
%A Lei Wu
%A Archit Gajjar
%A Han He
%T Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System
%J International Journal of Computer Applications
%@ 0975-8887
%V 180
%N 17
%P 1-7
%D 2018
%I Foundation of Computer Science (FCS), NY, USA

This paper presents a novel hierarchical synthesis for approximating field-programmable gate array (FPGA) based adders and multipliers. Our proposed work implements the multiplier design with the following contributions: 1) providing four types of single-bit approximate adders to cover a wide range of energy-quality tradeoffs, 2) presenting many approximations of multipliers by employing the single-bit adders, 3) substituting corresponding bits of the approximate multiplier by considering the quality constrains of the results. The novel hierarchical synthesis of the approach has been integrated into our prior project, an FPGA-IoTmesh system in the field of fog computing for hardware acceleration. Combining the merits of reconfigurability of FPGAs and long-distance connection of CSRmesh technology, this work creates a diverse range of applications such as approximate designs at the network edge, as well as showing a demo for Internet-of-Things (IoT) connections covering an entire building.

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Index Terms

Computer Science
Information Sciences


Approximate designs field-programmable gate array (FPGA) fog computing Internet-of-Things (IoT)