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Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2018
Authors:
Hadi Jahanirad
10.5120/ijca2018917136

Hadi Jahanirad. Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA. International Journal of Computer Applications 180(43):42-49, May 2018. BibTeX

@article{10.5120/ijca2018917136,
	author = {Hadi Jahanirad},
	title = {Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA},
	journal = {International Journal of Computer Applications},
	issue_date = {May 2018},
	volume = {180},
	number = {43},
	month = {May},
	year = {2018},
	issn = {0975-8887},
	pages = {42-49},
	numpages = {8},
	url = {http://www.ijcaonline.org/archives/volume180/number43/29422-2018917136},
	doi = {10.5120/ijca2018917136},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Soft errors such as Single Event Upset (SEU) have great effect on performance degradation of circuits implemented on SRAM_based FPGA. The soft error in configuration bits which control the logic and routing parts of the circuit, leads to permanent faults. In this paper, we have developed a co-evolutionary method to reduce the effect of soft error on the implemented circuit on FPGA. This method is based on cooperation of genetic algorithm and ant colony optimization. The efficiency of co-evolutionary method has been proved by comparison of its results with the proposed genetic algorithm and ant colony optimization. The experimental results for some MCNC benchmark circuits show up to 34% improvement compare to genetic algorithm and up to 60% improvement against ant colony optimization.

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Keywords

Soft error rate, SRAM_based FPGA, Place and route, GA, ACO