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FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

by Aniruddha Ghosh, Amitabha Sinha
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 181 - Number 14
Year of Publication: 2018
Authors: Aniruddha Ghosh, Amitabha Sinha
10.5120/ijca2018917785

Aniruddha Ghosh, Amitabha Sinha . FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis. International Journal of Computer Applications. 181, 14 ( Sep 2018), 9-22. DOI=10.5120/ijca2018917785

@article{ 10.5120/ijca2018917785,
author = { Aniruddha Ghosh, Amitabha Sinha },
title = { FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2018 },
volume = { 181 },
number = { 14 },
month = { Sep },
year = { 2018 },
issn = { 0975-8887 },
pages = { 9-22 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume181/number14/29889-2018917785/ },
doi = { 10.5120/ijca2018917785 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:05:57.409620+05:30
%A Aniruddha Ghosh
%A Amitabha Sinha
%T FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis
%J International Journal of Computer Applications
%@ 0975-8887
%V 181
%N 14
%P 9-22
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

New methodologies for efficiently describing and implementing digital systems are investigated as the complexity of binary digital hardware system is relentlessly expanding. From the recent study, it is shown that multi valued logic approach is more advantageous over existing binary digital system. Ternary means a multilevel switching component, which switches between 3 levels. Recent study on ternary number system (TNS), has shown numerous advantages over binary. In recent times, Double Base Number Systems (DBNS) are considered as alternatives to binary number system because of their capabilities of performing partial product free multiplications. On the other hand, Double Base Ternary Number System (DBTNS) multipliers are efficient compared to conventional TNS multiplier. High performance digital signal processing systems which can able to handle all Digital Signal Processing (DSP) algorithms, broadly utilize Multiply-Accumulate (MAC) operation. So, TNS Adder and DBTNS Multipliers can be used to implement fast MAC units. Keeping this in view, a new approach of designing efficient MAC unit using DBTNS multiplier is proposed in this work. The performance of proposed MAC unit is compared with conventional ternary multiplier-based MAC unit and they are mapped on a FPGA chip. Performance analysis clearly indicates that the supremacy of the proposed architecture over conventional ternary multiplier-based MAC unit.

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Index Terms

Computer Science
Information Sciences

Keywords

Ternary Number System (TNS) Trit Ternary Gates Ternary Arithmetic Double Base Ternary Number Systems (DBTNS) DBTNS Multiplier Multiply and Accumulate Unit (MAC) FPGA DSP Algorithms.

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