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Effective Techniques for Performance Enhancement on Embedded Multi-Processor Architectures

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2018
Hassan Salamy

Hassan Salamy. Effective Techniques for Performance Enhancement on Embedded Multi-Processor Architectures. International Journal of Computer Applications 181(17):25-33, September 2018. BibTeX

	author = {Hassan Salamy},
	title = {Effective Techniques for Performance Enhancement on Embedded Multi-Processor Architectures},
	journal = {International Journal of Computer Applications},
	issue_date = {September 2018},
	volume = {181},
	number = {17},
	month = {Sep},
	year = {2018},
	issn = {0975-8887},
	pages = {25-33},
	numpages = {9},
	url = {},
	doi = {10.5120/ijca2018917834},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


As the complexity of embedded applications is ever increasing, the trend in embedded architecture is to utilize a multi-processor system on a chip (MPSoC). MPSoCs provide the compute power and flexibility to effectively execute complex embedded systems. An embedded system often execute multiple complex embedded applications simultaneously. In this article, we tackle two main problems to further enhance the effective utilization of the embedded MPSoC architecture to reduce the execution time of the applications, namely, resource allocation and scheduling. We first present an effective resource allocator that examines the nature of the applications in the system to fairly allocate the fast on-chip scratchpad memory budget and the processing elements. Then this article presents an effective task scheduler that integrates scheduling and on-chip scratchpad memory partitioning for the maximum optimization of the system. Results on multiple real and synthetic benchmarks showed the effectiveness of our techniques.


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MPSoC, scratchpad, task scheduling, resource allocation.