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Effective Techniques for Performance Enhancement on Embedded Multi-Processor Architectures

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2018
Authors:
Hassan Salamy
10.5120/ijca2018917834

Hassan Salamy. Effective Techniques for Performance Enhancement on Embedded Multi-Processor Architectures. International Journal of Computer Applications 181(17):25-33, September 2018. BibTeX

@article{10.5120/ijca2018917834,
	author = {Hassan Salamy},
	title = {Effective Techniques for Performance Enhancement on Embedded Multi-Processor Architectures},
	journal = {International Journal of Computer Applications},
	issue_date = {September 2018},
	volume = {181},
	number = {17},
	month = {Sep},
	year = {2018},
	issn = {0975-8887},
	pages = {25-33},
	numpages = {9},
	url = {http://www.ijcaonline.org/archives/volume181/number17/29915-2018917834},
	doi = {10.5120/ijca2018917834},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

As the complexity of embedded applications is ever increasing, the trend in embedded architecture is to utilize a multi-processor system on a chip (MPSoC). MPSoCs provide the compute power and flexibility to effectively execute complex embedded systems. An embedded system often execute multiple complex embedded applications simultaneously. In this article, we tackle two main problems to further enhance the effective utilization of the embedded MPSoC architecture to reduce the execution time of the applications, namely, resource allocation and scheduling. We first present an effective resource allocator that examines the nature of the applications in the system to fairly allocate the fast on-chip scratchpad memory budget and the processing elements. Then this article presents an effective task scheduler that integrates scheduling and on-chip scratchpad memory partitioning for the maximum optimization of the system. Results on multiple real and synthetic benchmarks showed the effectiveness of our techniques.

References

  1. F. Angiolini, L. Benini, and A. Caprara. Polynomial-time algorithm for on-chip scratchpad memory partitioning. In Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2003.
  2. T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. IEEE Computer, 35(2), 2002.
  3. O. Avissar, R. Barua, and D. Stewart. An optimal memory allocation scheme for scratch-pad-based embedded systems. ACM Transactions on Embedded Computing Systems, 1(1), 2002.
  4. L. Benini, D. Bertozzi, A. Guerri, and M. Milano. Allocation and scheduling for mpsoc via decomposition and no-good generation. In Proc. International Joint conferences on Artificial Intelligence (IJCAI), 2005.
  5. S. Blagodurov, S. Zhuravlev, and A. Fedorova. Contention-aware scheduling on multicore systems. ACM Trans. Comput. Syst., 28(4), 2010.
  6. CPLEX. Ilog inc., ilog cplex 8.1 reference manual. http://www.ilog.com/products/cplex, 2008.
  7. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In Proc. IEEE 4th Annual Workshop on Workload Characterization, 2001.
  8. S.-R. Kuang, C.-Y. Chen, and R.-Z. Liao. Partitioning and pipelined scheduling of embedded systems using integer linear programming. In Proc. International Conference on Parallel and Distributed Systems (ICPADS), 2005.
  9. Y.-K. Kwok and I. Ahmad. Benchmarking and comparison of the task graph scheduling algorithms. Journal of Parallel and Distributed Computing, 59(3), 1999.
  10. C. Lee, M. Potkonjak, and W. Mangione-Smith. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proc. of IEEE International Symposium on Microarchitecture, pages 330 (335), 1997.
  11. G. D. Micheli, R. Ernst, and W. Wolf. Readings in hardware/software co-design. Morgan Kaufmann, 2002.
  12. P. Panda, N. Dutt, and A. Nicolau. Memory issues in embedded systems-on-chip: optimization and exploration. Kluwer Academics Publisher, 1999.
  13. P. Panda, N. D. Dutt, and A. Nicolau. On chip vs o_ chip memory: the data partitioning problem in embedded processor-based systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), 5(3), 2000.
  14. J. Sjodin and C. V. Platen. Storage allocation for embedded processors. In Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2001.
  15. S. Steinke, L. Wehmeyer, B.-S. Lee, and P. Marwedel. Assigning program and data objects to scratchpad for energy reduction. In Proc. Design Automation and Test in Europe (DATE), 2002.
  16. V. Suhendra, C. Raghavan, and T. Mitra. Integrated scratchpad memory optimization and task scheduling for mpsoc architecture. In Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2006.
  17. F. Sun, N. Jha, S. Ravi, and A. Raghnunathan. Synthesis of appication-specific heterogeneous multiprocessor architectures using extensible processors. In Proc. International Conference on VLSI Design, 2005.
  18. V. G. Vaidya, P. Ranadive, and S. Sah. Dynamic scheduler for multi-core systems. In 2nd International Conference on Software Technology and Engineering (ICSTE), 2010.
  19. L. Xue, O. Ozturk, F. Li, M. Kandemir, and I. Kolcu. Dynamic partitioning of processing and memory resources in embedded mpsoc architectures. In Proceedings of the conference on Design, automation and test in Europe (DATE), 2010.
  20. A. K. Coskun, T. S. Rosing, and K. A.Whisnant. Temperature aware task scheduling in mpsocs. In Proceedings of Design, Automate and Test in Europe Conference and Exhibition (DATE), 2007.
  21. Y. Xie and W.-L. Hung. Temperature-aware task allocation and scheduling for embedded multiprocessor systems-on-chip (mpsoc) design. Journal of VLSI Signal Processing, 45:177(189), 2006.
  22. J. Chen, C. Yang, T. Kuo, and C. Shih. Energy-efficient real-time task scheduling in multiprocessor dvs systems. In Proc. Asia and South Pacific Design Automation Conference, 2007.
  23. Q. Tang, S. K.S.Gupta, and G. Varsamopoulos. Energy-efficient thermal-aware task scheduling for homogeneous high performance computing data centers:a cyber-physical approach. IEEE Transactions on Parallel and Distributed Systems, 19:1458-1472, 2008.
  24. K. Kanoun, N. Mastronarde, D. Atienza, and M. V. D. Schaar. Online energy-efficient task-graph scheduling for multicore platforms. IEEE Transactions on Computer Aided Design, 33(8), 2014.
  25. P.-H. Tseng, P.-C. Hsiu, C.-C. Pan, and T.-W. Kuo. User-centric energy-efficient scheduling on multi-core mobile devices. In Design Automation Conference (DAC), 2014.
  26. R. P. Dick, D. L. Rhodes, and W. Wolf, “Tgff: Task graphs for free,” in the 6th International Workshop on Hardware/Software Codesign, 1998, pp. 97–101.

Keywords

MPSoC, scratchpad, task scheduling, resource allocation.