The week's pick
Reseach Article
Design and Implementation of Conventional D Flip-Flop for Registers
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 181 - Number 39 |
| Year of Publication: 2019 |
| Authors: A. Lakshmi, P. Chandrasekhar Reddy |
10.5120/ijca2019918392
|
A. Lakshmi, P. Chandrasekhar Reddy . Design and Implementation of Conventional D Flip-Flop for Registers. International Journal of Computer Applications. 181, 39 ( Jan 2019), 24-28. DOI=10.5120/ijca2019918392
Abstract
More than 50% of random logic power in an SOC chip is typically consumed by Flip Flop. This is because of redundant transition of internal nodes, when the input and output appear to be in the same state. Different low power techniques have been proposed, but all of these designs use more transistors. Leading to an increase in size, which is too costly since flip flops typically account for 50% of random logic area. In this paper we design D flip-flop using 2x1 multiplexer which has reduced transistor count compared to other low power designs of D flip-flops. The focus is to design high speed, low power consumption, positive edge triggered conventional D flip-flop which can be used for registers in multipliers. In this paper the D flip-flop is modified in such a way that it controls the overall capacitances during the operation and will optimize the total capacitance that results in the decrease of the Average Power dissipation. The flip-flop is realized using only 8 transistors. The circuit is characterized by using cadence tools in 0.18 µm technology.
References
- Massoud Pedram., 1995 Design Technologies for Low Power VLSI, Encyclopedia of Computer Science and Technology,
- Gray Yeap and Gilbert, 1998 Practical Low power Digital VLSI Design, Kluwer Academic Publishers.
- Rabaey.J, 2003 Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice-Hall.
- Pedram, . 1996,Power Minimization in IC Design, ACM Transactions on Design Automation of Electronic Systems, Vol 1, No. 1, pp. 3-56
- Jui-Ming Chang and Massoud Pedram. 1997,Energy Minimization Using Multiple Supply Voltages", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 4, Pp: 436-444,
- J. P. Fishburn and A. E. Dunlop, 1985, TILOS: a posynomial programming approach to transistor sizing,” in Proceedingsof the International Conference on computer Aided Design(ICCAD ’85),
- Yu Chien-Cheng “Design of Low-Power Double Edge- Triggered Flip- Flop Circuit” 2007 Second IEEE Conference on Industrial Electronics and Applications 23-25 May 2007 pp 2054-2057
- Nedovic, N. Aleksic, M. Oklobdzija, V.G. “ Comparative analysis of double-edge versus single-edge triggered clocked storage elements” Circuits and Systems 2002, ISCAS 2002.,IEEE International Symposium
- Vladimir Stojanovic andVojin G.Oklobdzija, Comparative, “Analysis of Master-Slave Latches and Flip-Flops for High–Performance and Low- Power System,” IEEE J. Solid-State Circuits, vol.34, pp.536-548, April 1999.
- R. Hossain, L. D. Wronski, and A. Albicki, "Low power design using double edge triggered flip-flops," IEEE Trans. on VLSI Systems, vol. 2, no. 2, pp. 261-265, June 1994.
- Yiran Li, Tie Sun, Xiaodong Yang, Zhenming Zhou “A Comparative Analysis of Single Edge-Triggered & Dual Edge-Triggered Flip-Flops”
- N.H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, 2nd ed. Reading MA: Addison-Wesley, 1993
- Gary K.Yeap, Practical Low power Digital VLSI Design, Kluwer Academic Publishers, 1998.
- Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and Design 3RD Edition TATA McGRAW HILL.
Index Terms
Keywords