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Reversible Logic gate based on QSD Addition/Subtraction using DPG Gate

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2019
Asiya Hasan, Nishi Pandey, Meha Shrivastava

Asiya Hasan, Nishi Pandey and Meha Shrivastava. Reversible Logic gate based on QSD Addition/Subtraction using DPG Gate. International Journal of Computer Applications 182(47):42-45, April 2019. BibTeX

	author = {Asiya Hasan and Nishi Pandey and Meha Shrivastava},
	title = {Reversible Logic gate based on QSD Addition/Subtraction using DPG Gate},
	journal = {International Journal of Computer Applications},
	issue_date = {April 2019},
	volume = {182},
	number = {47},
	month = {Apr},
	year = {2019},
	issn = {0975-8887},
	pages = {42-45},
	numpages = {4},
	url = {},
	doi = {10.5120/ijca2019918723},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


Arithmetic Logic Unit plays a vital role in the central processing unit of the computer system. Addition is considered to be a primary part in the ALU. Power and speed are the major parameters to be kept in mind for designing an adder. Because of carry propagation, complexity and delay gets introduced in the adder circuit due to which addition, subtraction and multiplication obtains delay in the Arithmetic Logic unit. In order to reduce the delay, carry-free addition is introduced by QSD (Quaternary Signed Digit) Numbers. In this paper, a fast QSD Addition and Subtraction circuit is designed by use of DPG Reversible Logic Gates.


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Quaternary Signed Digit (QSD), Reversible Gate, DPG Gate, Carry Free Addition