Call for Paper - December 2020 Edition
IJCA solicits original research papers for the December 2020 Edition. Last date of manuscript submission is November 20, 2020. Read More

Reversible Logic gate based on QSD Addition/Subtraction using DPG Gate

Print
PDF
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2019
Authors:
Asiya Hasan, Nishi Pandey, Meha Shrivastava
10.5120/ijca2019918723

Asiya Hasan, Nishi Pandey and Meha Shrivastava. Reversible Logic gate based on QSD Addition/Subtraction using DPG Gate. International Journal of Computer Applications 182(47):42-45, April 2019. BibTeX

@article{10.5120/ijca2019918723,
	author = {Asiya Hasan and Nishi Pandey and Meha Shrivastava},
	title = {Reversible Logic gate based on QSD Addition/Subtraction using DPG Gate},
	journal = {International Journal of Computer Applications},
	issue_date = {April 2019},
	volume = {182},
	number = {47},
	month = {Apr},
	year = {2019},
	issn = {0975-8887},
	pages = {42-45},
	numpages = {4},
	url = {http://www.ijcaonline.org/archives/volume182/number47/30513-2019918723},
	doi = {10.5120/ijca2019918723},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Arithmetic Logic Unit plays a vital role in the central processing unit of the computer system. Addition is considered to be a primary part in the ALU. Power and speed are the major parameters to be kept in mind for designing an adder. Because of carry propagation, complexity and delay gets introduced in the adder circuit due to which addition, subtraction and multiplication obtains delay in the Arithmetic Logic unit. In order to reduce the delay, carry-free addition is introduced by QSD (Quaternary Signed Digit) Numbers. In this paper, a fast QSD Addition and Subtraction circuit is designed by use of DPG Reversible Logic Gates.

References

  1. Simranjeet Singh Sudan and Manish Singhal, “MIG and COG Reversible Logic gate Based QSD Addition / Subtraction”, International Conference on Computing, Communication and Automation (ICCCA2017).
  2. Radhika Thakur, Shruti Jain and Meenakshi Sood, FPGA Implementation of Unsiged Multiplier Circuit based on Quaternary Signed Digit Number System”, IEEE Conference on Signal Processing, Computing and Control, IEEE 2017.
  3. Purva Agarwal and Pawan Whig, “Low Delay Based 4 Bit QSD Adder / Subtraction Number System By Reversible Logic Gate”, 2016 8th International Conference on Computational Intelligence and Communication Networks.
  4. Ameya N. Bankar, Shweta Hajare, “Design of Arithmetic Circuit Using Quaternary Signed Digit Number System”, International Conference on Communication and Signal Processing, April 3-5, 2014, India.
  5. Tanay Chattopadhyay and Tamal Sarkar, “Logical Design of Quaternary Signed Digit Conversion Circuit and its Effectuation using Operational Amplifier”, Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, December 2012.
  6. Krishna Murthy, Gayatri G, Manoj Kumar “Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate” VLSICS Vol.3, No.3, June 2012.
  7. M. D. Saiful Islam and Z. Begum, Reversible Logic Synthesis Of Fault Tolerant Carry Skip BCD Adder, Journal of Bangladesh Academy of Sciences, Vol. 32, No. 2, 193-200, 2008.
  8. M. K. Thomsen, R. Gluck, H. B. Axelsen, 2010, Reversible arithmetic logic unit for quantum arithmetic, Journal of physics A: Mathematical and Theoretical, 43 (2010) 382002 (10pp), doi: 10.1088/1751- 8113/43/38/382002.
  9. M. Haghparast, K. Navi, 2008: A Novel Fault Tolerant Reversible Gate For Nanotechnology Based Systems, Am. J. Applied Sci., 5(5), 519-523.
  10. B. Parhami, Fault Tolerant Reversible Circuits, Proc. Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA,Oct.2006.
  11. Haghparast, M. and K. Navi, “ A novel fault tolerant reversible gate for nanotechnology based systems”. Am. J. Appl. Sci., 5(5).2008.
  12. Jayashree H V and Ashwin S, “Berger Check and Fault Tolerant Reversible Arithmetic Component Design”, 978-1- 4799 - 8364-3/ 15/ $31.00 @ 2015 IEEE

Keywords

Quaternary Signed Digit (QSD), Reversible Gate, DPG Gate, Carry Free Addition