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Reseach Article

DPA to Rectify Transient Faulty Nodes in Effective Manner

by P. S. Balamurugan, K.Thanushkodi
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 19 - Number 5
Year of Publication: 2011
Authors: P. S. Balamurugan, K.Thanushkodi

P. S. Balamurugan, K.Thanushkodi . DPA to Rectify Transient Faulty Nodes in Effective Manner. International Journal of Computer Applications. 19, 5 ( April 2011), 11-18. DOI=10.5120/2359-3088

@article{ 10.5120/2359-3088,
author = { P. S. Balamurugan, K.Thanushkodi },
title = { DPA to Rectify Transient Faulty Nodes in Effective Manner },
journal = { International Journal of Computer Applications },
issue_date = { April 2011 },
volume = { 19 },
number = { 5 },
month = { April },
year = { 2011 },
issn = { 0975-8887 },
pages = { 11-18 },
numpages = {9},
url = { },
doi = { 10.5120/2359-3088 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T20:06:11.421560+05:30
%A P. S. Balamurugan
%A K.Thanushkodi
%T DPA to Rectify Transient Faulty Nodes in Effective Manner
%J International Journal of Computer Applications
%@ 0975-8887
%V 19
%N 5
%P 11-18
%D 2011
%I Foundation of Computer Science (FCS), NY, USA

Wireless sensor networks faces a number of challenges; a wireless sensor network which includes a number of sensor nodes must provide reliability and fault tolerance against a number of odds such as scalability, hardware, environmental conditions, power and energy factors. In this paper, we address these two issues of Reliability and Fault Tolerance using mirror nodes. We demonstrate that increased reliability can be achieved by using mirror nodes and the costs could be maintained by implementing the Direct Processor Access(DPA). Experimental results on the benchmarks data set show that our proposed system based on Direct Processor Access outperforms the other well-known methods such as the Distributed Deviation Detection, Distributed anomaly detection, Intrusion detection for routing attacks, Statistical en route filtering and Abnormal Relationship Tests(ART). The improvement in performance using DPA is very high, particularly, for the graphical and network processes (6.8 percent improvement). Statistical Tests also demonstrate higher fault tolerance and improvement in performance for our method. Finally, we show that our system is robust and is able to handle faulty sensor nodes without compromising performance.

  1. E. Rohou and M. Smith, (1999), “Dynamically managing processor temperature and power,” Proc. FDDO-2
  2. S. I. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat,(2000) “Multiple Si layer ICs: Motivation, performance analysis, and design implications,” Proc Design Automation Conf., pp. 873-880.
  3. S. Das, A. Chadrakasan, (2003) “Three-dimensional integrated circuits: performance, design methodology, and CAD tools,” Proc. IEEE Annual Symp. on VLSI,pp. 13-18.
  4. M.B. Kleiner, S. A. Kuhn, P. Ramm and W. Weber,(1995) “Thermal analysis of vertically integrated circuits.” Tech. Dig. Int’l Electron Devices Meeting, pp.487-490.
  5. A. Rahman, R. Reif, (2001) “Thermal analysis of three dimensional (3-D) integrated circuits (ICs),” Proc.Int’l Interconnect Technology Conf., pp. 157-159.
  6. F. Fallah and M. Pedram,(2005) "Standby and active leakage current control and minimization in CMOS VLSI circuits." IEICE Trans. on Electronics, Special Section on Low-Power LSI and Low-Power IP, Vol. E88-C, No. 4, pp. 509-519.
  7. B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, and S. Borkar, (2003) “Effectiveness and scaling trends of leakage control techniques for sub-100nm CMOS technologies,” Proc. Int’l Symp. Low-power Electronics, pp. 122-127.
  8. M.L. Mui, K. Banerjee, A. Mehrota, (2004) “Power supply optimization in sub-130nm leakage dominant technologies,” Proc. Int’l Symp. Quality Electronic Design, pp. 409-414.
  9. Int’l Technology Roadmap for Semiconductors (ITRS), 2004.
  10. K. Banerjee, A. Mehrotra, A. Sangiovanni- Vincentelli, and C. Hu (1999) “On Thermal Effects in Deep Sub-Micron VLSl Interconnects,” Proc. Design Automation Conf. , pp. 885-891.
  11. H. J. M. Veendrick (1984) “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE Journal of Solid-State Circuits, vol. 19, pp. 468–473.
  12. A. Alvandpour, P.L. Edefors, C. Svensson, (1998) “Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits,” Proc. Low Power Electronics and Design, pp. 245-249.
  13. S. Turgis, N. Azemard, and D. Auvergne, (1996) “Explicit evaluation of short-circuit power dissipation and its influence on propagating delay for static CMOS gates,” Proc. IEEE Int. Symp. on Circuits and Systems,vol. 4, pp. 751-754.
  14. S.H. Jung, J.H. Baek, S.Y. Kim, (2001) “Short circuit power estimation of static CMOS circuits,” Proc. Asia- Pacific Design Automation Conf., pp. 545-549.
  15. P.S.Balamurugan, K.Thanushkodi, (2009) “Array Cache An Efficient Memory For Multi Core Processor”, Kyoto Journal of Engineering Research, Vol XI, 0024-609X
Index Terms

Computer Science
Information Sciences


Wireless Sensor Networks Faulty Sensor Nodes Fault Tolerance Direct Processor Access Mirror Nodes