CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Application Specific Data Trace Cache Design

by Sunita Parashar, Anshu Parashar
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 22 - Number 5
Year of Publication: 2011
Authors: Sunita Parashar, Anshu Parashar
10.5120/2580-3565

Sunita Parashar, Anshu Parashar . Application Specific Data Trace Cache Design. International Journal of Computer Applications. 22, 5 ( May 2011), 18-21. DOI=10.5120/2580-3565

@article{ 10.5120/2580-3565,
author = { Sunita Parashar, Anshu Parashar },
title = { Application Specific Data Trace Cache Design },
journal = { International Journal of Computer Applications },
issue_date = { May 2011 },
volume = { 22 },
number = { 5 },
month = { May },
year = { 2011 },
issn = { 0975-8887 },
pages = { 18-21 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume22/number5/2580-3565/ },
doi = { 10.5120/2580-3565 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:08:37.433893+05:30
%A Sunita Parashar
%A Anshu Parashar
%T Application Specific Data Trace Cache Design
%J International Journal of Computer Applications
%@ 0975-8887
%V 22
%N 5
%P 18-21
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Increasing disparity between processor speeds and memory access times is a major problem in today’s systems. In this paper we have studied the design of a proposed system i.e. An Application specific Data Trace Cache and have tried to do some modification to the Data Remapping portion of it. We have tried to further improve the benefits of this system by implementing this system with the help of an already existing concept of Cache Conscious Data Structures. Reference locality of data can be improved by changing a program’s data organization and layout. This is the concept behind both cache conscious data structures as well as Data Trace Cache. So we have tried to merge both these strategies to get some more performance benefits.

References
  1. Krishna V. Palem and Rodric M. Rabbah . Design Space Exploration and Optimization of Embedded Cache Systems via a Compiler. In ACM Transactions in Embedded Computing Systems.
  2. Eric Rotenberg, Steve Bennett, James E. Smith 1996. Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching . In the Proceedings of the 29th Annual International Symposium on Microarchitecture.
  3. Chen Ding, Ken Kennedy 1999. Improving Cache Performance in Dynamic Applications through Data and Computation Reorganization at Run Time. SIGPLAN ‘99 (PLDI) Atlanta, GA,
  4. D. Callahan, S. Carr, and K. Kennedy 1990. Improving register allocation for subscripted variables. In Proceedings of the SIGPLAN ‘90 Conference on Programming Language Design and Implementation, White Plains, NY.
  5. M. E. Wolf and M. Lam 1991. A data locality optimizing algorithm. In Proceedings of the SIGPLAN ’91 Conference on Programming Language Design and Implementation, Toronto, Canada.
  6. W. Abu-Sufah, D. Kuck, and D. Lawrie 1981. On the performance enhancement of paging systems through program analysis and transformations. IEEE Transactions on computers, C-30(5):341-356.
  7. D. Gannon, W. Jalby, and K. Gallivan 1987. Strategies for cache and local memory management by global program transformations. In Proceedings of the First International Conference on Supercomputing. Springer-Verlag, Athens, Greece.
  8. K. S. McKinley, S. Carr, and C.-W. Tseng. Improving data locality with loop transformations. ACM Transactions on Programming Languages and Systems
  9. M. Cierniak and W. Li 1995. Unifying data and control transformations for distributed share d-memory machines. In Proceedings of the SIGPLAN ’95 Conference on Programming Language Design and Implementation, La Jolla.
  10. R. M. Rabbah and K. V. Palem 2003. Data remapping for design space optimization of embedded memory systems. ACM Transactions in Embedded Computing Systems.
  11. Trishul M. Chilimbi, Bob Davidson, and James R. Larus. 1999.Cache-conscious structure definition. In Proceedings of the ACM SIGPLAN’99 Conference on Programming Language Design and Implementation.
  12. Intel Itanium 2 Processor Hardware Developer’s Manual, 2002.
  13. Subramanian Ramaswamy, Jaswanth Sreeram, Sudhakar Yalamanchili, K. V. Palem 2005. Data Trace Cache: An Application Specific Cache Architecture . In MEDEA 2005 workshop in conjunction with PACT 2005.
  14. Intel IXP2800 Network Processor Hardware Reference Manual, 2002
  15. Trishul M. Chilimbi, Mark D. Hill, James R. Larus 1999. Cache-Conscious Structure Layout . . In Proceedings of the SIGPLAN ’99 Conference on Programming Language Design and Implementation, Atlanta.
Index Terms

Computer Science
Information Sciences

Keywords

Trace Cache Cache Conscious data structure reference locality

Powered by PhDFocusTM