The week's pick
Reseach Article
Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 22 - Number 7 |
| Year of Publication: 2011 |
| Authors: Pavan.T.K, Jagannadha Naidu.K, Nagaraju.V |
10.5120/2599-3613
|
Pavan.T.K, Jagannadha Naidu.K, Nagaraju.V . Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption. International Journal of Computer Applications. 22, 7 ( May 2011), 1-7. DOI=10.5120/2599-3613
Abstract
As process technology shrinks, the adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power applications. In order to minimize total active power consumption in digital circuits, one must take into account sub-threshold leakage currents that grow exponentially as technology scales. This describes to predict how dynamic power and sub-threshold power must be balanced. The exclusive supply voltage control switching makes stable operations. The threshold voltage control successfully maintains a ratio of switching to leakage current and which represents the reduced power consumption. The goal of this paper is to: i) Maintains the optimized body bias conditions. ii) Maintains the best power-delay tradeoff. The results with a 180-nm CMOS device explain that the proposed architecture causes in the successful optimization of power.
References
- Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, yoetsu Nakazawa, “Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold Voltage control in active and standby modes”, in IEEE Journal of solid state circuits, vol.41, Apr.2006, pp. 805-814.
- V. R. von Kaenel, M. D. Pardoen, E. Dijkstra, and E. A. Vittoz, “Automatic adjustment of threshold and supply voltages for minimum power consumption in CMOS digital circuits,” in IEEE Symp. Low Power Electronics Dig. Tech. Papers, Oct. 1994, pp. 78–79.
- J. T. Kao, M. Miyazaki, and A. P. Chandrakasan, “A 175-mV multiply accumulate unit using an adaptive supply voltage and body bias architecture,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1545–1554, Nov. 2002.
- K. Nose and T. Sakurai, “Optimization of VDD and VTH for low power and high-speed applications,” Proc. ASP-DAC, pp. 469–474, Jan. 2000.
- T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, “Variable supply volt zoltage scheme for low power high speed CMOS digital design,” IEEE J. of solid state Circuits, vol.33,pp.454-462, Mar.2003.
- C. Neau and K. Roy, “Optimal body bias selection for leakage improvement and process compensation over different technology generations,” in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2003, pp. 116–121.
- M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kuwahara, K. Kumano, and M. Shimura, “Dynamic voltage and frequency management for a low-power embedded microprocessor,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28–35, Jan. 2005.
- M. Nomura, Y. Ikenaga, K. Takeda, , Y. Aimoto, and Y. Hagihara, “Monitoring scheme for minimizing power consumption by means of supply and threshold voltage control in active and standby modes,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 308–311.
- R. Kumar, C.P. Ravikumar, "Leakage power estimation for deep submicron circuits in an ASIC design environment", Design Automation Conference on VLSI Design, ASP-DAC 2002, 7-1 1 Jan. 2002, pp. 45 - 50.
- K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-sub micrometer CMOS circuits", IEEE, Vol. 91, No. 2, Feb. 2003, pp. 305 - 327.
- O. Semenov, A. Pradzynski, M. Sachdev, "Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits", IEEE Transactions on Semiconductor Manufacturing, Vol. 15, No. 1, Feb. 2002, pp. 9 - 18.
Index Terms
Keywords