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Article:Efficient Modular Adders for Scalable Encryption Algorithm
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 23 - Number 4 |
| Year of Publication: 2011 |
| Authors: K.J. Jegadish Kumar, K.Chenna Kesava, S. Salivahanan |
10.5120/2880-3750
|
K.J. Jegadish Kumar, K.Chenna Kesava, S. Salivahanan . Article:Efficient Modular Adders for Scalable Encryption Algorithm. International Journal of Computer Applications. 23, 4 ( June 2011), 1-5. DOI=10.5120/2880-3750
Abstract
Scalable Encryption algorithm (SEA) is a symmetric block cipher, specially designed for resources constrain systems like, sensor nodes, RFIDs and other ultra low power operated portable devices. SEA proposes low cost encryption routines (i.e. small code size, memory and power), targeted for processors with a limited instruction set. SEA is parametric with text, key and processor size, and allows efficient combination of encryption/decryption and key derivation. In this paper, we investigate the performance of SEA using efficient architectures of 2b and 2b-1 modular adders in a Field programmable gate array (FPGA) device. For this purpose, an iterative loop design of the block cipher is first implemented on FPGA. Beyond its low cost performances, the proposed architecture is fully flexible with any parameters and takes advantage of generic VHDL coding. Our efficient modular adders’ implementation achieves lower area and power consumption on the target platform VIRTEX-4, xc4vl25 -10ff668.
References
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