CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

An Analog Architecture for Split-Radix DHT

by Gautam A. Shah, Tejmal S. Rathore
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 30 - Number 4
Year of Publication: 2011
Authors: Gautam A. Shah, Tejmal S. Rathore
10.5120/3630-5069

Gautam A. Shah, Tejmal S. Rathore . An Analog Architecture for Split-Radix DHT. International Journal of Computer Applications. 30, 4 ( September 2011), 24-31. DOI=10.5120/3630-5069

@article{ 10.5120/3630-5069,
author = { Gautam A. Shah, Tejmal S. Rathore },
title = { An Analog Architecture for Split-Radix DHT },
journal = { International Journal of Computer Applications },
issue_date = { September 2011 },
volume = { 30 },
number = { 4 },
month = { September },
year = { 2011 },
issn = { 0975-8887 },
pages = { 24-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume30/number4/3630-5069/ },
doi = { 10.5120/3630-5069 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:16:05.601405+05:30
%A Gautam A. Shah
%A Tejmal S. Rathore
%T An Analog Architecture for Split-Radix DHT
%J International Journal of Computer Applications
%@ 0975-8887
%V 30
%N 4
%P 24-31
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The fast Hartley transform and algorithm for DHT was introduced by Bracewell. The split radix decimation-in-frequency algorithm that requires less number of operation counts as compared to the radix-2 and radix-4 algorithms was developed by Sorenson et al. In this paper, an analog architecture for a split radix decimation-in-time algorithm is proposed. It utilizes three different structures in the signal flow diagram. It exhibits a recursive pattern and is modular. The validity of the analog architecture is tested by simulating it with the help of the Orcad PSpice.

References
  1. Paik, C. H. and Fox, M. D. 1988. Fast Hartley transform for image processing, IEEE Trans. Medical Imaging, vol. 7, no. 2, (June 1988), pp. 149-153.
  2. Wu, J. L. and Shiu, J. 1991. Discrete Hartley transform in error control coding,” IEEE Trans. Signal Processing, vol. 39, no. 10, (Oct. 1991), pp. 2356-2359.
  3. Meher, P. K. and Panda, G. 1993. Unconstrained Hartley-domain least mean square adaptive filter,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 40, no. 9, (Sep. 1993), pp. 582-585.
  4. Meher, P. K., Srikanthan, T. and Patra, J. C. 2006. Scalable and modular memory-based systolic architectures for discrete Hartley transform, IEEE Trans. Circuits Syst. I, vol. 53, no. 5, (May 2006), pp. 1065–1077.
  5. Hartley, R. V. L. 1942. A more symmetrical Fourier analysis applied to transmission problems, Proc. IRE, vol. 30, (Mar. 1942), pp. 144-150.
  6. Bracewell, R. N. 1984. The fast Hartley transform,” Proc. IEEE, vol. 72, no. 8, (Aug. 1984), pp. 1010-1018.
  7. Meckelburg, H. J. and Lipka, D. 1985. Fast Hartley transform algorithm, Electronics Letters, vol. 21, no. 8, (Apr. 1985), pp. 311-313.
  8. Prado, J. 1985. Comments on “The fast Hartley transform,” Proc. IEEE, vol. 73, no. 12, (Dec. 1985), pp. 1862-1863.
  9. Kwong, C. P. and Shiu, K. P. 1986. Structured fast Hartley transform algorithms, IEEE Trans. Acoustics, Speech, and Signal Processing, vol. ASSP-34, no. 4, (Aug. 1986), pp. 1000-1002.
  10. Hou, H. S. 1987. The Fast Hartley Transform Algorithm, IEEE Trans. Computers, vol. C-36, no. 2, (Feb 1987), pp. 147-156.
  11. Malvar, H. S. 1987. Fast computation of the discrete cosine transform and the discrete Hartley transform, IEEE Trans. Acoustics, Speech, and Signal Processing, vol. ASSP-35, no. 10, (Oct. 1987), pp. 1484-1485.
  12. Hao, H. 1987. On fast Hartley transform algorithms, Proc. IEEE, vol. 75, no. 7, (July 1987), pp. 961-962.
  13. Rathore, T. S. 1989. Recursive relations for complexities of Hartley transform algorithms, IETE J. of Research, vol. 35, no. 6, (Nov.-Dec 1989), pp. 357-359.
  14. Rathore, T. S. 1990. Hartley transform – Properties and algorithms, In Proceedings of the Nat. Conf. Real Time Systems, Indore, (Nov. 1990), pp. 21-30.
  15. Bracewell, R. N. 1986. The Hartley transform, New York: Oxford University Press.
  16. Sorensen, H. V., Jones, D. L., Burrus, C. S. and Heideman, M. T. 1985. On computing the discrete Hartley transform, IEEE Trans. Acoustics, Speech, and Signal Processing, vol. ASSP-33, no. 4, (Oct. 1985), pp. 1231-1238.
  17. Culhane, A. D., Peckerar, M. C. and Marrian, C. R. K. 1989. A neural net approach to discrete Hartley and Fourier transforms, IEEE Trans. Circuits Syst., vol. 36, no. 5, (May 1989), pp. 695-703.
  18. Raut, R., Bhattacharya, B. B. and Faruque, S. M. 1990. A discrete Fourier transform using switched-capacitor circuits in systolic array architecture, IEEE Trans. Circuits Syst., vol. 37, no. 12, (Dec. 1990), pp. 1578-1580.
  19. Kawahito, S. et al. 1997. A CMOS image sensor with analog two-dimensional DCT based compression circuits for on-chip cameras, IEEE J. Solid-State Circuits, vol. 32, no. 12, (Dec. 1997), pp. 2030-2041.
  20. Chen, J., Shou, G., and Zhou, C. 1999. Digital-controlled analog circuits for weighted-sum operations, IEICE Trans. Fundamentals, vol. E82-A, no. 11, (Nov 1999), pp. 2505-2513.
  21. Mal, A. K. and Dhar, A. S. 2003. Analog Sampled Data Architecture for Discrete Hartley Transform, In Proceedings of the Tenth Int. Conf. on Convergent Technologies for Asia-Pacific Region, Bangalore, India, vol. 3, (Oct. 2003), pp. 1035–1039.
  22. Gift, S. J. G. and Maundy, B. 2005. Improving the Bandwidth Gain-Independence and Accuracy of the Current Feedback Amplifier, IEEE Trans. Circuits Syst. II, vol. 52, no. 3, (Mar. 2005), pp. 136-139.
  23. Madian, A. H., Mahmoud, S. A. and Soliman, A. M. 2008. Field Programmable Analog Array based on CMOS CFOA and its Application, In Proceedings of the IEEE Int. Conf. Electr. Circuits Syst. (Aug.-Sept. 2008), pp. 1042–1046.
  24. AD-844 data sheet, Monolithic operational amplifier, Analog Devices, Rev-C.
  25. Rathore, T. S. and Khot, U. P. 2008. CFA-based grounded-capacitor operational simulation of ladder filters, Int. J. Circ. Theor. Appl., vol. 36, no. 5-6, (July 2008), pp. 697-716.
  26. Shah, G. A. and Rathore, T. S. 2011. A Mixed-Mode Signal Processing Architecture for Radix-2 DHT, Int. J. Computer Science and Engineering, vol. 3, no. 6, (June 2011), pp. 2554-2564.
Index Terms

Computer Science
Information Sciences

Keywords

Decimation-in-time Radix-2 Radix-4 Split-Radix

Powered by PhDFocusTM