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Evolutionary design and optimization of digital Circuits using Imperialist Competitive Algorithm

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International Journal of Computer Applications
© 2011 by IJCA Journal
Number 1 - Article 1
Year of Publication: 2011
Authors:
Mehdi Anjomshoa
Ali Mahani
Mostafa Esmaeil beig
10.5120/3868-5404

Mehdi Anjomshoa, Ali Mahani and Mostafa Esmaeil Beig. Article: Evolutionary Design and Optimization of Digital Circuits using Imperialist Competitive Algorithm. International Journal of Computer Applications 32(1):14-19, October 2011. Full text available. BibTeX

@article{key:article,
	author = {Mehdi Anjomshoa and Ali Mahani and Mostafa Esmaeil Beig},
	title = {Article: Evolutionary Design and Optimization of Digital Circuits using Imperialist Competitive Algorithm},
	journal = {International Journal of Computer Applications},
	year = {2011},
	volume = {32},
	number = {1},
	pages = {14-19},
	month = {October},
	note = {Full text available}
}

Abstract

This paper describes the application of Imperialist Competitive Algorithm (ICA) to design and optimization of combinational logic circuits. Imperialist Competitive Algorithm is a new socio-politically motivated global search strategy that recently has been introduced for dealing with different optimization tasks. We proposed a cost function to evolve circuits at gate level with lower number of transistors. By decreasing the total number of transistors, the area of circuit will be optimized too. The performance of the proposed algorithm is evaluated using different circuits from literature. The simulation results clearly demonstrate the validity of this new technique. We can consider this heuristic algorithm as a search engine in evolutionary hardware applications.

Reference

  • D. Chen, T. Aoki, N. Homma, T. Terasaki & T. Higuchi, “Graphbased evolutionary design of arithmetic circuits. IEEE Transaction on Evolution and Computation, Vol. 6, No. 1, pp. 86–100, 2002.
  • Shuguang Zhao, Study of the Evolutionary Design Methods of Electronic Circuits, Ph.D. dissertation (in Chinese), Xidian University, 2003.
  • C. Y. Chen & R. C. Hwang, "A new variable topology for evolutionary hardware design", Expert Systems With Applications, Vol. 36, No. 1, pp. 634-642, 2009.
  • M. Karnaugh, A map method for synthesis of combinational logic circuits, Transactions of the AIEE, Communications and Electronics, 72(I):593- 599, November 1953.
  • E.J. McCluskey, Minimisation of Boolean functions, Bell Systems Technical Journal, 35(5):1417-1444, November 1956.
  • C. A. Coello, A. D. Christiansen, and A. H. Aguirre, “Use of evolutionary techniques to automate the design of combinational circuits”, Int. J. Smart Engineering System Design 2 (4), 299–314 (2001).
  • C. A. Coello, A. D. Christiansen, and A. H. Aguirre, “Automated design of combinational logic circuits using genetic algorithms”, Proc. Int. Conf. on Artificial Neural Nets and Genetic Algorithms, 335–338 (1997).
  • C. A. Coello, A. H. Aguirre, and B. P. Buckles, “Evolutionary multiobjective design of combinational logic circuits”, Proc. 2nd NASA/DoD Workshop on Evolvable Hardware, 161–170 (2000).
  • A. Słowik and M. Białko, “Design and optimization of combinational digital circuits using modified evolutionary algorithm”, Proc. 7th Int. Conf. on Artifficial Intelligence and Soft Computing 3070, 468–473 (2004).
  • A. Słowik and M. Białko., “Evolutionary design and optimization of combinational digital circuits with respect to transistor count”, Bulletin of the Polish Academy of Sciences,Technical Sciences Vol. 54, No. 4, 2006.
  • P. Nilagupta and N. Ou-thong, “Logic function minimization base on transistor count using genetic algorithm”, Proc. 3rd Information and Computer Engineering Postgraduate Workshop, Songkla, Thailand, 2003.
  • E. Atashpaz-Gargari and C. Lucas, “Imperialist Competitive Algorithm: An Algorithm for Optimization Inspired by Imperialistic Competition,” IEEE Congress on Evolutionary Computation (CEC 2007). pp 4661-6447, 2007.
  • Lucas, C., Nasiri-Gheidari, Z., Tootoonchian, F. "Application of an imperialist competitive algorithm to the design of a linear induction motor”. Energy Conversion and Management 51(7): 1407–1411, 2010.
  • Mozafari, Hamid; Abdi, Behzad; Ayob, Amran. "Optimization of Transmission Conditions for Thin Interphase Layer Based on Imperialist Competitive Algorithm". (IJCSE) International Journal on Computer Science and Engineering 2 (7): 2486–2490, 2010.
  • H. Sayadnavard, Monireh; T. Haghighat, Abolfazl; Abdechiri, Marjan "Wireless sensor network localization using Imperialist Competitive Algorithm". 3rd IEEE International Conference on Computer Science and Information Technology, 2010.
  • S. J. Louis, G. J. E. & Rawlins, G. J. E., “Designer genetic algorithms: Genetic algorithms in structure design”, Fourth international conference on genetic algorithms. San Mateo, CA: Morgan Kauffman, pp. 53–60, 1991.
  • G. Petley. ASIC standard cell library design. http://www.vlsitechnology.org/.