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A Survey of High-Level Synthesis Techniques for Area, Delay and Power Optimization

International Journal of Computer Applications
© 2011 by IJCA Journal
Number 1 - Article 1
Year of Publication: 2011
S.M. Logesh
D. S. Harish Ram
M.C. Bhuvaneswari

S M Logesh, Harish D S Ram and M C Bhuvaneswari. Article:A Survey of High-Level Synthesis Techniques for Area, Delay and Power Optimization. International Journal of Computer Applications 32(10):1-6, October 2011. Full text available. BibTeX

	author = {S.M. Logesh and D. S. Harish Ram and M.C. Bhuvaneswari},
	title = {Article:A Survey of High-Level Synthesis Techniques for Area, Delay and Power Optimization},
	journal = {International Journal of Computer Applications},
	year = {2011},
	volume = {32},
	number = {10},
	pages = {1-6},
	month = {October},
	note = {Full text available}


With increasing complexity of digital signal processing VLSI circuits in recent decades, design methodologies and tools have moved to higher abstraction levels. High level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power of the circuit are mutually conflicting thereby necessitating trade-offs between different objectives. The electronic system-level (ESL) paradigm facilitates exploration, synthesis, and verification that can handle the complexity of today’s system-on-chip (SoC) designs. Processor customization and High Level Synthesis have become necessary paths to efficient ESL design. This paper presents the survey of high level synthesis approaches and methodologies for simultaneous area, delay and power optimization.


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