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Hardware Architecture for a Message Hiding Algorithm with Novel Randomizers

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 37 - Number 7
Year of Publication: 2012
Authors:
Saeed Mahmoudpour
Sattar Mirzakuchaki
10.5120/4623-6632

Saeed Mahmoudpour and Sattar Mirzakuchaki. Article: Hardware Architecture for a Message Hiding Algorithm with Novel Randomizers. International Journal of Computer Applications 37(7):46-53, January 2012. Full text available. BibTeX

@article{key:article,
	author = {Saeed Mahmoudpour and Sattar Mirzakuchaki},
	title = {Article: Hardware Architecture for a Message Hiding Algorithm with Novel Randomizers},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {37},
	number = {7},
	pages = {46-53},
	month = {January},
	note = {Full text available}
}

Abstract

Steganography is the art of hiding information in a cover medium such that the existence of information is concealed. An image is a suitable cover medium for steganography because of its great amount of redundant spaces. One simple method of image steganography is the replacement of the least significant bit (LSB) of a cover image with a message bit. This represents a high embedding capacity but it is detectable by statistical analysis methods such as Regular-Singular (RS) and Chi-square analyses. Therefore, a new LSB algorithm is proposed here which can effectively resist statistical analysis. In this novel algorithm, every two sample’s LSB bits are combined using addition modulo 2 which is compared to the secret message. If these two values are not equal, their difference is added to the second sample. Otherwise, no change is made. This paper proposes a hardware realization of this new algorithm. Furthermore, two scalable pixel interleaver and novel message bit randomizer with two different stego-keys are designed. Pixel interleaver can improve resistance against visual analysis by random selection of pixels.

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