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Reseach Article

NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol

by Nitin Kumar Tiwari, Ravi Kumar, R. K. Sarin, Sarabjeet Singh
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 43 - Number 20
Year of Publication: 2012
Authors: Nitin Kumar Tiwari, Ravi Kumar, R. K. Sarin, Sarabjeet Singh
10.5120/6221-8786

Nitin Kumar Tiwari, Ravi Kumar, R. K. Sarin, Sarabjeet Singh . NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol. International Journal of Computer Applications. 43, 20 ( April 2012), 26-30. DOI=10.5120/6221-8786

@article{ 10.5120/6221-8786,
author = { Nitin Kumar Tiwari, Ravi Kumar, R. K. Sarin, Sarabjeet Singh },
title = { NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol },
journal = { International Journal of Computer Applications },
issue_date = { April 2012 },
volume = { 43 },
number = { 20 },
month = { April },
year = { 2012 },
issn = { 0975-8887 },
pages = { 26-30 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume43/number20/6221-8786/ },
doi = { 10.5120/6221-8786 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:33:55.746245+05:30
%A Nitin Kumar Tiwari
%A Ravi Kumar
%A R. K. Sarin
%A Sarabjeet Singh
%T NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol
%J International Journal of Computer Applications
%@ 0975-8887
%V 43
%N 20
%P 26-30
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

System on Chip Wire (SoCWire) is a Network on Chip (NoC) based design that composed of intellectual property blocks (IP) and interconnects based on space wire standard, was successfully implemented in Venus Express Monitoring Camera (VMC) mission and proposed to implement in Solar Orbital mission in future. The efficient and accurate implementation of SoCWire is the main concern in this work. A solution for single bit error detection and correction with hamming code for 8 bit data has been proposed, so that the accuracy of the design is improved with cost of extra resources and we can save nearly 19. 2 ?s time that is required to link re-initialization also the speed of the design is improved compared to conventional Codec. For routing data of many codec from one node to many other nodes SoCWire Switch is implement with crossbar based switch for 8 ports and achieved maximum frequency 179. 743 MHz and 5% device utilization can be saved compared to [1]. These functionality and design performance are achieved with coding level change in VHDL for SoCWire. The design is synthesized on Xilinx ISE 12. 1. The Target FPGA is XCVLX-60 which belongs to Xilinx Virtex 4 QPro.

References
  1. B. Osterloh, "SoCWire User Manual", www. socwire. org, 2009.
  2. Sudeep Pasricha, Nikil Dutt, "On-Chip Communication Architectures", Morgan Kaufmann Publications, U. S, 2008.
  3. P. Guerrier and A. Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections," Proc. Design, Automation and Test in Europe (DATE '00), pp. 250-256, Mar. 2000.
  4. ECSS, Space Engineering: SpaceWire–Links, nodes, routers, and networks, ESA-ESTEC, Noordwijk Netherlands, ECSS-E-50-12A, (January 2003).
  5. SM Parkes "ECSS, Space Engineering: SpaceWire:SERIAL POINT-TO POINT LINKS", ESA- ESTEC, , Dundee, ECSS-E-50-12A,(January 2000).
  6. Bjorn Osterloh, Harald Michalik, Björn Fiethe, Frank Bubenhagen "Architecture Verification of the SoCWire NoC Approach for Safe Dynamic Partia Reconfiguration in Space Applications" NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2011), Sep 2010.
  7. U. K. Kumar, B. S Umashankar "Improved Hamming Code for Error Detection and Correction", ISWPC, pp. 498-500, 2007.
  8. U. K. Kumar, B. S Umashankar "Improved Hamming Code for Error Detection and Correction" ISWPC-2007.
  9. Simon Tam, "Single Error Correction and Double Error Detection", Application Note: Virtex-II Pro, Virtex-4, and Virtex-5 Families, Xilinx XAPP645 (v2. 2) August 9, 2006.
  10. B. Osterloh, H. Michalik, B. Fiethe, F. Bubenhagen, "Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application", AHS'07. pp. 258-262, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, August 2007.
  11. B. Osterloh, H. Michalik, B. Fiethe, K. Kotarowski, "SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications", NASA/ESA Conference on Adaptive Hardware and Systems, (AHS-2010), 2010
Index Terms

Computer Science
Information Sciences

Keywords

Socwire Hamming Code Crossbar And Packet