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Reseach Article

Design of Low Power RISI Processor by Applying Clock Gating Technique

by J. Ravindra, T. Anuradha
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 43 - Number 20
Year of Publication: 2012
Authors: J. Ravindra, T. Anuradha
10.5120/6223-8819

J. Ravindra, T. Anuradha . Design of Low Power RISI Processor by Applying Clock Gating Technique. International Journal of Computer Applications. 43, 20 ( April 2012), 38-42. DOI=10.5120/6223-8819

@article{ 10.5120/6223-8819,
author = { J. Ravindra, T. Anuradha },
title = { Design of Low Power RISI Processor by Applying Clock Gating Technique },
journal = { International Journal of Computer Applications },
issue_date = { April 2012 },
volume = { 43 },
number = { 20 },
month = { April },
year = { 2012 },
issn = { 0975-8887 },
pages = { 38-42 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume43/number20/6223-8819/ },
doi = { 10.5120/6223-8819 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:33:57.039867+05:30
%A J. Ravindra
%A T. Anuradha
%T Design of Low Power RISI Processor by Applying Clock Gating Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 43
%N 20
%P 38-42
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Power has become a primary consideration during hardware design. Dynamic power can contribute up to 50% of the total power dissipation. Clock-gating is the most common RTL optimization for reducing dynamic power. Effective clock-gating implementation requires skilful application and comprehensive verification. Clock-gating support adds additional logic to the existing synchronous circuit to prune the clock tree, thus disabling the portions of the circuitry that are not in use. Here in this project designed and developed efficient data path and control units of an 8-bit microprocessor and clock gating technique applied to designed units. RTL clock-gating algorithms can be grouped into three categories: system-level, sequential and combinational. System-level clock-gating stops the clock for an entire block, effectively disabling all functionality. On the contrary, combinational and sequential clock-gating selectively suspend clocking while the block continues to produce output. In typical designs, combinational clock-gating can reduce dynamic power by about 5-to-10%. On the other hand sequential clock-gating can save significant power, typically reducing switching activity by 15-to-25% on a given block. Thus, different RTL techniques are used to reduce the power dissipation of a processor. The whole paper captured in VHDL and implemented on targeted FPGA chip and observed the power using Xilinx Xpower tool

References
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Index Terms

Computer Science
Information Sciences

Keywords

Embedded Systems Vhdl Clock-gating Low Power