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Reconfigurable Architecture for Network processing

by A. Kaleel Rahuman, G. Athisha
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 43 - Number 9
Year of Publication: 2012
Authors: A. Kaleel Rahuman, G. Athisha
10.5120/6135-8371

A. Kaleel Rahuman, G. Athisha . Reconfigurable Architecture for Network processing. International Journal of Computer Applications. 43, 9 ( April 2012), 43-49. DOI=10.5120/6135-8371

@article{ 10.5120/6135-8371,
author = { A. Kaleel Rahuman, G. Athisha },
title = { Reconfigurable Architecture for Network processing },
journal = { International Journal of Computer Applications },
issue_date = { April 2012 },
volume = { 43 },
number = { 9 },
month = { April },
year = { 2012 },
issn = { 0975-8887 },
pages = { 43-49 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume43/number9/6135-8371/ },
doi = { 10.5120/6135-8371 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:33:01.069088+05:30
%A A. Kaleel Rahuman
%A G. Athisha
%T Reconfigurable Architecture for Network processing
%J International Journal of Computer Applications
%@ 0975-8887
%V 43
%N 9
%P 43-49
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The high performance of an elliptic curve (EC) crypto system depends efficiently on the arithmetic in the underlying finite field. We have to propose and compare two levels of Galois Field GF(2163) and GF(2193). The proposed architecture is based on Lopez-Dehab elliptic curve point multiplication algorithm, which uses Gaussian normal basis for GF(2163) field arithmetic. In which derived parallelized elliptic curve point doubling and addition algorithms with uniform addressing are based on Lopez-Dehab method. The proposed GF(2193) is based on an efficient Montgomery add and double algorithm, also the karatsuba-offman multiplier and Itoh-Tsjuii algorithm are used as the inverse component. The hardware design is based on optimized Finite State Machine(FSM), with a single cycle 193 bits multiplier, field adder and field squarer . The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication; increases frequency and the speed of operation such as key generation, encryption and decryption. Finally we have to implement our design using Xilinx XC4VLX200 FPGA device.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Elliptic Curves Cryptography Ecc Fpga Montgomery Karatsuba-offman Galois Field Operations

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