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Software Defined Radio Equipment: What's the Best Design Approach to Reduce Power Consumption and Increase Reconfigurability?

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 45 - Number 14
Year of Publication: 2012
Authors:
Manel Hentati
Amor Nafkha
Pierre Leray
Mohamed Abid
Jean-françois Nezan1
10.5120/6850-9417

Manel Hentati, Amor Nafkha, Pierre Leray, Mohamed Abid and Jean-françois Nezan1. Article: Software Defined Radio Equipment: What's the Best Design Approach to Reduce Power Consumption and Increase Reconfigurability?. International Journal of Computer Applications 45(14):26-32, May 2012. Full text available. BibTeX

@article{key:article,
	author = {Manel Hentati and Amor Nafkha and Pierre Leray and Mohamed Abid and Jean-françois Nezan1},
	title = {Article: Software Defined Radio Equipment: What's the Best Design Approach to Reduce Power Consumption and Increase Reconfigurability?},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {45},
	number = {14},
	pages = {26-32},
	month = {May},
	note = {Full text available}
}

Abstract

This article explores several hardware design methods used to implement a reconfigurable software defined radio system. The promise of software defined radios for rapidly changing the operating characteristics of radios suggests further an exciting new method to create opportunities and means for interoperability among and between any number of different radio systems. The possibilities of run-time reconfiguration techniques are explained and quantified. In this article, we are going to limit our discussion to examine the reconfigurability and low power trade-offs between: (i) building dedicated functional modules providing high performance at a high cost (Velcro approach), versus (ii) parameterizable function blocks used in FPGA-based system development, versus (iii) dynamic partial reconfiguration which is the ability to reconfigured a portion of the FPGA while the remainder is still in operation. The main objective here is to explore and discuss the best method to design a reconfigurable, a high performance and a low power consumption software defined equipment.

References

  • J. H. Reed, "Software Radio Modern Approach to Radio Engineering ", Prentice Hall, Upper Saddle River,NJ 13-18, 2002.
  • H Lee and all, "Software Defined Radio - A High Performance Embedded Challenge ", , Intl. Conference on High Performance Embedded Architecture and Compiler. 2005.
  • F. ~Jondral Software Defined Radio Enabling Technologie (by Walter Tuttlebee), book, chapter Parametrization - A technique for SDR Implementation. Wiley, 2002. .
  • J. Palicot, C. ~Roland FFT: a basic Function for a Reconfigurable Receiver, ICT'2003, Papeete, Tahiti,Feb. 2003. .
  • V. Rodriguez, C. Moy, J. Palicot, Install or invoke?: The optimal trade-off between performance and cost in the design of multi-standard reconfigurable radios, Wiley InterScience, Wireless Communications and Mobile Computing Journal, to appear, 2007.
  • P. Elias Coding for Noisy Channels, IRE Conv. Rec. , Part 4, pp. 37-47, 1955.
  • A. J. Viterbi Error bounds for convolutional codes and an asymptotically optimum decoding algorithm, IEEE Trans. Inf. Theory, vol. IT-13, pp. 260-269, Apr 1967.
  • Diana Gohringer, Jonathan Obie, André, L. S. Braga, Michael Hubner, Carlos H. Llanos, and Jurgen Becker "Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems", International Journal of Reconfigurable Computing Volume 2011.
  • P. Manet, and all An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications, EURASIP Journal on Embedded Systems, 2008. .
  • P. Lysaght, B. Blodget, J. Mason, B. Bridgford, and J. Young Enhanced Architectures, Design Methodologies and CAD Tools for dynamic reconfiguration of XILINX FPGAs, in 16th Int. Conf. on Field Programmable Logic and Applications (FPL2006), pp. 12-17, 2006. .
  • Cindy Kao Benefits of Partial Reconfiguration Take advantage of even more capabilities in your FPGA, Xcell Journal Xilinx, vol. I, pp. 65-67, 2005. .
  • V. Rodriguez, C. Moy, and J. Palicot An optimal architecture for a multi-standard reconfigurable radio: Cost-minimising common operators under latency constraints}, IST Mobile Summit'06, Mykonos : Greece, 2006. .
  • J. Delorme, A. Nafkha, P. Leray, and C. Moy , New OPBHWICAP interface for real-time partial reconfiguration of FPGA}, ReConFig'09, Cancun : Mexico. 2009.
  • Y. Thonnart, E. Beigne, and P. Vivet, Design and Implementation of a GALS Adapter for ANoC Based Architectures, ASYNC'09, pp. 13-22, 2009.
  • S. Liu, R. N Pittman, and A. Forin, Energy reduction with run-time partial reconfiguration, in Proc. FPGA, 2010.
  • R. V. Kshirsagar and S. Sharma, difference based partial reconfiguration, International Journal of Advances in Engineering and Technology, Vol. 1,Issue 2,pp. 194-197, May 2011. .
  • Two flows for Partial Reconfiguration: Module Based or Difference based, xilinx Application Note XAPP290 (v2. 0) December 3, 2007.
  • B. Krill, A. Ahmad, A. Amira, and H. Rabah, An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores}, Journal of Signal Proc. : Image Comm. , vol. 25(5), pp. 377-387, 2010.
  • MicroBlaze Processor Reference Guide Embedded Development Kit EDK 10. 1i, UG081 (v9. 0), 2008.
  • www. xilinx. com.
  • Wemekamp, John, Emerging Trends in Mil/Aerospace Embedded Systems, Electronic Component News, pp. 27-29, May 2007.