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Reseach Article

Low Power and Small Area Implementation for OFDM Applications

by K. Umapathy, D. Rajaveerappa
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 45 - Number 9
Year of Publication: 2012
Authors: K. Umapathy, D. Rajaveerappa
10.5120/6810-9158

K. Umapathy, D. Rajaveerappa . Low Power and Small Area Implementation for OFDM Applications. International Journal of Computer Applications. 45, 9 ( May 2012), 35-38. DOI=10.5120/6810-9158

@article{ 10.5120/6810-9158,
author = { K. Umapathy, D. Rajaveerappa },
title = { Low Power and Small Area Implementation for OFDM Applications },
journal = { International Journal of Computer Applications },
issue_date = { May 2012 },
volume = { 45 },
number = { 9 },
month = { May },
year = { 2012 },
issn = { 0975-8887 },
pages = { 35-38 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume45/number9/6810-9158/ },
doi = { 10.5120/6810-9158 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:37:11.493404+05:30
%A K. Umapathy
%A D. Rajaveerappa
%T Low Power and Small Area Implementation for OFDM Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 45
%N 9
%P 35-38
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper proposes that several FFT algorithms such as radix-2, radix-4 and split radix were designed using VHDL with the multiplication complexity reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers and the simulations of standard 0. 35 ?m. The sizes of FFT/IFFT operations are varied in different applications of OFDM systems. The reorganized Mixed Radix 4-2 Butterfly FFT with bit reversal for the output sequence derived by index decomposition execution is our suggested VLSI system architecture to design the module FFT/IFFT processor for OFDM systems. The output shows that the proposed processor architecture can minimize the area cost while keeping a high-speed processing speed, a decrement of more than 70% of the power consumption/area when compared with complex multiplier

References
  1. Bruno Fernandes , Helena Sarmento "Implementation of an 128 FFT for a MB-OFDM Receiver" 978-972-789-304-1 REC'2010 page no 45-48
  2. Tai-cheng Lee,Yen-chuan Huang" The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application" solid state circuits. IEEE journal v41,Isu 6 page no. 1253-1261.
  3. "A High-Speed Low-Complexity Modified FFT Processor for High Rate WPAN Applications "Very Large Scale Integration (VLSI) Systems, IEEE Transactions on volu :pp,Issue :99 page no 1-5
  4. K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parhi, "Design of low-error fixed-width modified booth multiplier," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 12, no. 5, pp. 522–531, 2004.
  5. Shousheng. He and Mats Torkelson, "Design and Implementation of a 1024-point Pipeline FFT Processor", IEEE Custom Integrated Circuits Conference, May. 1998, pp. 131-134.
  6. Shousheng He and Mats Torkelson, "Designing Pipeline FFT Processor for OFDM (de)Modulation", IEEE Signals, Systems, and Electronics, Sep. 1998, pp. 257-262.
  7. Shousheng He and Mats Torkelson, "A New Approach to Pipeline FFT Processor", IEEE Parallel Processing Symposium, April. 1996, pp. 776-780.
  8. C. Sidney Burrus, "Index Mapping for Multidimensional Formulation of the DFT and Convolution", IEEE Trans. Acoust. , Speech, and Signal Processing, Vol. ASSP-25, June. 1977,pp. 239-242.
  9. Lihong Jia, Yonghong GAO, Jouni Isoaho, and Hannu Tenhunen, "A New VLSI-Oriented FFT Algorithm and Implementation", IEEE ASIC Conf. , Sep. 1998, pp. 337-341.
  10. Martin Vetterli and Pierre Duhamel, "Split-Radix Algorithms for Length-ptmDFT's", IEEE Trans. Acoust, Speech, and Signal Processing, Vol. 37, No. 1, Jan. 1989, pp. 57-64.
  11. Daisuke Takahashi, "An Extended Split-Radix FFT Algorithm", IEEE Signal Processing Letters, Vol. 8, No. 5, May. 2001, pp. 145-147.
  12. Y. T. Lin, P. Y. Tsai, and T. D. Chiueh, "Low-power variable-length fast Fourier transform processor", IEE Proc. Comput. Digit. Tech, Vol. 152, No. 4, July. 2005, pp. 499-506.
  13. Byung G. Jo and Myung H. Sunwoo, "New Continuous-Flow Mixed-Radix (CFMR) FFT Processor Using Novel In-Place Strategy", IEEE Transactions on Circuits and Systems, Vol. 52, No. 5, May. 2005.
  14. Gordon L. Demuth, "Algorithms for Defining Mixed Radix FFT Flow Graphs", IEEE Trans Acoust, Speech, and Signal Processing, Vol. 37, No. 9, Sept. 1989, pp. 1349-1358.
  15. Kyung L. Heo, Jae H. Baek, Myung H. Sunwoo, Byung G. Jo, and Byung S. Son, "New In-Place Strategy for a Mixed-Radix FFT processor", IEEE SOC Conference, Sep. 2003, pp. 8 1-84.
  16. S. He and M. Torkelson, "Designing pipeline FFT processor for OFDM (de) modulation," Proc. IEEE URSI Int. Symp. Signals, Syst. , Electron. , pp. 257–262, 1998.
  17. J. Melander, Design of SIC FFT Architectures, Link¨oping Studies in Science and Technology, Thesis no. 618, Link¨oping University, Sweden, 1997.
  18. J. Y. Oh, J. S. Cha, S. K. Kim, and M. S. Lim, "Implementation of orthogonal frequency division multiplexing using radix-N pipeline fast Fourier transform (FFT) processor," Jpn. J. Appl. Phys. 1, vol. 42, Regul. Pap. Short Notes, no. 4B, pp. 1–6, 2003.
  19. K. K. Parhi, VLSI digital signal processing systems, John Wiley & Sons, USA, 1999.
  20. S. M. Kim, J. G. Chung, and K. K. Parhi, "Design of low error CSD fixed-width multiplier," IEEE Inter. Symp. Cir. , Syst. , vol. 1, pp. I-69–I-72, 2002. 2002.
Index Terms

Computer Science
Information Sciences

Keywords

Fft/ifft Ofdm Radix24 Radix22 Multiplier