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A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures

International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 47 - Number 3
Year of Publication: 2012
H. Chtioui
S. Niar Lamih
R. Ben-Atitallah
M. Zahran
Jl. Dekeyser
M. Abid

H Chtioui, Niar S Lamih, R Ben-Atitallah, M.Zahran, Jl. Dekeyser and M Abid. Article: A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures. International Journal of Computer Applications 47(3):45-50, June 2012. Full text available. BibTeX

	author = {H. Chtioui and S. Niar Lamih and R. Ben-Atitallah and M.Zahran and Jl. Dekeyser and M. Abid},
	title = {Article: A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {47},
	number = {3},
	pages = {45-50},
	month = {June},
	note = {Full text available}


Nowadays, Multi-Processor System-on-Chip (MPSoC) have become an essential solution for embedded applications. In this paper we focus on MPSoCs using shared-memory programming model, which facilitates the programmer task. Moreover, one of the main factors affecting the performance of such systems is the management of cache coherency problem. In this context, we propose a new cache-coherency protocol. The proposed protocol is able to dynamically adapt its functioning mode according to variations in application memory access patterns. Experimental results show that with four cores, the new protocol reduces the number of cache misses by 77%, which results in 20% reduction in execution time and 34% decrease in the total energy consumption.


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