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A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 47 - Number 3
Year of Publication: 2012
Authors:
H. Chtioui
S. Niar Lamih
R. Ben-Atitallah
M. Zahran
Jl. Dekeyser
M. Abid
10.5120/7172-9801

H Chtioui, Niar S Lamih, R Ben-Atitallah, M.Zahran, Jl. Dekeyser and M Abid. Article: A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures. International Journal of Computer Applications 47(3):45-50, June 2012. Full text available. BibTeX

@article{key:article,
	author = {H. Chtioui and S. Niar Lamih and R. Ben-Atitallah and M.Zahran and Jl. Dekeyser and M. Abid},
	title = {Article: A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {47},
	number = {3},
	pages = {45-50},
	month = {June},
	note = {Full text available}
}

Abstract

Nowadays, Multi-Processor System-on-Chip (MPSoC) have become an essential solution for embedded applications. In this paper we focus on MPSoCs using shared-memory programming model, which facilitates the programmer task. Moreover, one of the main factors affecting the performance of such systems is the management of cache coherency problem. In this context, we propose a new cache-coherency protocol. The proposed protocol is able to dynamically adapt its functioning mode according to variations in application memory access patterns. Experimental results show that with four cores, the new protocol reduces the number of cache misses by 77%, which results in 20% reduction in execution time and 34% decrease in the total energy consumption.

References

  • D. Jhalani, D. Palsetia, "Adaptive cache coherence protocol using migratory shared data", 2007.
  • D. J. L. Farnaz Mounes-Toussi, "The potential of compile-time analysis to adapt the cache coherence enforcement strategy to the data sharing characteristics", in: IEEE Transactions on Parallel and Distributed Systems, May 1995, p. 6(5) :470.
  • J. R. Goodman, "Using cache memory to reduce processor-memory traffic", in: Proceedings of the 10th Annual International Symposium on Computer Architecture, June 1983, pp. 124{131.
  • J. K. Archibald, "A cache coherence approach for large multiprocessor systems", In Proceedings of the 2nd International Conference on Supercomputing, France, July 1988, pp. pages 337{345.
  • H. Grahn, P. Stenstrom, M. Dubois, "Implementation and evaluation of update-based cache protocols under relaxed memory consistency models", in: Future Generation Computer Systems, June 1995, pp. 11(3) :247{ 271.
  • F. Dahlgren, M. Dubois, P. Stenstrm, "Sequential hardware prefetching in shared-memory multiprocessors", in :IEEE Trans. Parallel and Distributed Systems, 733-746, July 1995, pp. vol. 6, no. 7.
  • F. Dahlgren, " Performance evaluation and cost analysis of cache protocol extensions for shared-memory multiprocessors", in : IEEE Transactions on Computers, october 1998, pp. I, vol. 47, no. 10.
  • H. Chtioui, R. Ben Atitallah, S. Niar, J. L. Dekeyser, M. Abid, "A dynamic hybrid cache coherency protocol for shared-memory mpsoc", in 12th Euromicro Conference On Digital System Design Architectures, Methods and Tools (DSD'09), Patras, Greece, 27-29 August, 2009.
  • L. M. Censier, P. Feautrier, "A new solution to coherence problems in multicache systems", in: IEEE Transactions on Computers, December 1978.
  • SoCLib, "An integrated system-on-chip modeling and simulation platform", 2003. technical report, cnrs,.
  • R. Sendag, A. Yilmazer, J. J. Yi, A. K. Uht, "Quantifying and reducing the effects of wrong-path memory references in cache-coherent multi-processor systems", in : Parallel and Distributed Processing Symposium, April 2006