Call for Paper - November 2023 Edition
IJCA solicits original research papers for the November 2023 Edition. Last date of manuscript submission is October 20, 2023. Read More
International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 47 - Number 6
Year of Publication: 2012
![]() |
10.5120/7192-9949 |
S Subha. Article: Energy Efficient Fully Associative Cache Model. International Journal of Computer Applications 47(6):16-18, June 2012. Full text available. BibTeX
@article{key:article, author = {S. Subha}, title = {Article: Energy Efficient Fully Associative Cache Model}, journal = {International Journal of Computer Applications}, year = {2012}, volume = {47}, number = {6}, pages = {16-18}, month = {June}, note = {Full text available} }
Abstract
Energy consumption in caches depends on the number of enabled sets/ways/blocks. The optimal energy consumption is the case of one set/one way/one block enabled. This paper proposes an algorithm to map cache line to one block in fully associative cache by XOR'ing the address with constant. Bit selection is applied to the result and the block accessed. Only one block is accessed in this mapping. The proposed model is simulated with SPEC2K benchmarks. The average memory access time is comparable with traditional fully associative cache with energy savings.
References
- A. J. Smith, Cache memories, ACM Computing Surveys, Vol. 14 No. 3, pp. 473-530, September 1982
- Antonio Gonzalez, Mateo Valero, Nigel Topham, Joan. M. Parcerisa, Eliminating Cache Conflict Misses Through XOR-Based Placement Functions, Proceedings of International Conference on Supercomputing, 1997, pp. 76-83
- Chuanjun Zhang, Frank Vahid, Jun Yang and Walid Najjar, A Way-Halting Cache for Low-Energy High Performance Systems, ACM Transactions on Architecture and Code Optimization, Vol. 2, No. 1, March 2003, pp. 34-54
- David. A. Patterson and John. L. Hennessy, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 3rd Edition, 2003
- David. H. Albonesi, Selective Cache Ways: On demand cache resource Allocation, Proceedings of International Symposium on Microarchitecture, 1999
- G. Rivera, C. W. Tseng, Data Transformations for Eliminating Conflict Misses, PLDI, 1998
- Huiyang Zhou, Mark. C. Toburen, Eric Rotenberg, Thomas. M. Conte, Adaptive Mode Control: A Static-Power-Efficient Cache Design, ACM Transactions on Embedded Computing Systems, Vol. 2, No. 3, August 2003, pp. 347-372
- Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim, Power-aware deterministic block allocation for low-power way-selective cache structure, Proceedings of ICCD, 2004
- Michael. D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy, Reducing set-associative cache energy via way-prediction and selective direct mapping, Proceedings of MICRO, 2001
- RuiMin, Zhiyong Xu, Yiming Hu, Wen-ben Jone, Partial tag comparison: a new technology for power-efficient set-associative cache designs, Proceedings of 17th International Conference on VLSI Design, 2004, pp. 183-188
- S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, E. Geethanjali, Power-aware partitioned cache architectures, Proceedings of ISPLED, 2001, pp. 64-67
- S. Subha, Set Associative Cache Model with Energy Saving, Proceedings of ITNG, 2008, pp. 1249-1250
- S. Subha, An Algorithm for Fully Associative Cache Memory, Proceedings of Second Bihar Science Conference, 2009
- S. Subha, Performance Analysis of Variable number of Sets in Fully Associative Cache, Proceedings of ICC, 2009, pp. 295-298
- Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi, Improving Cache Power Efficiency with an Asymmetric Set Associative Cache, Proceedings of Workshop of Memory Performance, 2001