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Four Stage Pipelined 16 bit RISC on Xilinx Spartan 3AN FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 48 - Number 6 |
| Year of Publication: 2012 |
| Authors: Aboobacker Sidheeq.v.m |
10.5120/7352-0093
|
Aboobacker Sidheeq.v.m . Four Stage Pipelined 16 bit RISC on Xilinx Spartan 3AN FPGA. International Journal of Computer Applications. 48, 6 ( June 2012), 29-38. DOI=10.5120/7352-0093
Abstract
This paper describes the design and implementation of a 16 bit 4 stage pipelined Reduced Instruction Set Computer (RISC) processor on a Xilinx Spartan 3AN Field programmable gate array (FPGA). The processor implements the Harvard memory architecture, so the instruction and data memory spaces are both physically and logically separate. The RISC processor architecture presented in this paper is designed by six units, they are instruction cache, instruction unit, decode unit, execute unit, data cache unit and register file unit. The processor has been described using Verilog HDL, simulated using ModelSim 6. 5-SE simulator and synthesized using Xilinx ISE 11. 1i. The proposed processor has been implemented and physically tested Xilinx FPGA Spartan 3AN development board, It uses ChipScope Pro 9. 2i embedded logic analyzer to monitor any or all of the signals in the design.
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