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Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 50 - Number 19
Year of Publication: 2012
Authors:
Dinesh Chand Gupta
Ashish Raman
10.5120/7910-1150

Dinesh Chand Gupta and Ashish Raman. Article: Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology. International Journal of Computer Applications 50(19):18-22, July 2012. Full text available. BibTeX

@article{key:article,
	author = {Dinesh Chand Gupta and Ashish Raman},
	title = {Article: Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {50},
	number = {19},
	pages = {18-22},
	month = {July},
	note = {Full text available}
}

Abstract

Limited energy consumption in multimedia requires very low power circuits. In this paper we focused on leakage current minimization in single static random access memory (SRAM) cell in 90nm complementary metal oxide semiconductor (CMOS) technology. The leakage current mainly consists of sub threshold leakage current and gate leakage current in 90nm CMOS technology. So minimizing the sub threshold leakage current and gate leakage current is most important aspect in low power memory design. This work presents a technique based on dual threshold voltage (Vt), dual gate oxide thickness (tox) and dual power supply (Vdd) assignment together to minimize gate leakage and sub threshold current of SRAM cell. Simulation results using 90nm CMOS technology show that this technique can reduce the total leakage current dissipation of a single SRAM cell by more than 75% with less delay penalty.

References

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