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Architecture Design and FPGA Implementation of an FFT based Reactive Power Meter

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 50 - Number 9
Year of Publication: 2012
Authors:
Msr Naidu
G. R Locharla
Gbsr Naidu
10.5120/7801-0926

Msr Naidu, G r Locharla and Gbsr Naidu. Article: Architecture Design and FPGA Implementation of an FFT based Reactive Power Meter. International Journal of Computer Applications 50(9):32-34, July 2012. Full text available. BibTeX

@article{key:article,
	author = {Msr Naidu and G.r Locharla and Gbsr Naidu},
	title = {Article: Architecture Design and FPGA Implementation of an FFT based Reactive Power Meter},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {50},
	number = {9},
	pages = {32-34},
	month = {July},
	note = {Full text available}
}

Abstract

Reactive power measurement is increasingly paid attention by power industry. A novel architecture to measure the reactive power is proposed in this paper. Architecture is described in verilog and implemented using Xilinx ISE 13. 1i. In this method voltage and current signals in time domain are converted to the frequency domain and power on each component is calculated to obtain the total reactive power.

References

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