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Design and Optimization of Reversible Multiplier Circuit

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 52 - Number 10
Year of Publication: 2012
Authors:
Rangaraju H. G
Aakash Babu Suresh
Muralidhara K. N
10.5120/8242-1523

Rangaraju H.g, Aakash Babu Suresh and Muralidhara K.n. Article: Design and Optimization of Reversible Multiplier Circuit. International Journal of Computer Applications 52(10):44-50, August 2012. Full text available. BibTeX

@article{key:article,
	author = {Rangaraju H.g and Aakash Babu Suresh and Muralidhara K.n},
	title = {Article: Design and Optimization of Reversible Multiplier Circuit},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {52},
	number = {10},
	pages = {44-50},
	month = {August},
	note = {Full text available}
}

Abstract

The development of conventional computing technologies faces many challenges for the last couple of decades. Power dissipation in today's computer chips becomes dominant. Reversible computing is a promising alternative to these technologies, with applications in ultra-low power, nano computing, quantum computing, low power CMOS design, optical information processing, bioinformatics etc. In reversible logic the power dissipation can be minimized or even eliminated. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM gate. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct nxn reversible multiplier circuit.

References

  • R Landauer, 1961. Irreversibility and Heat Generation in the Computational Process. IBM Journal of Research and Development, vol. 5, no. 3, pp. 183-191.
  • C H Bennett, 1973. Logical Reversibility of Computation. IBM Journal of Research and Development, vol. 17, no. 6, pp. 525-532.
  • Kerntopf P, M A Perkowski and M H A Khan, 2004. On Universality of General Reversible Multiple Valued Logic Gates. Proceedings of the Thirty Fourth IEEE International Symposium on Multiple valued Logic, pp. 68 – 73.
  • Richard P Feynman, 1985. Quantum Mechanical Computers. Optics News, vol. 11, issue 2, pp. 11-20.
  • T Toffoli, 1980. Reversible Computing. Technical Memo MIT/LCS/TM-151, MIT Lab for Computer Science.
  • Edward Fredkin and Tommaso Toffoli, 1982. Conservative Logic. International Journal of Theoretical Physics, vol. 21, pp. 219-253.
  • A Peres, 1985. Reversible Logic and Quantum Computers. International Journal on Physical Review a General Physics, vol. 32, no. 6, pp. 3266–3276.
  • William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, and Marek Perkowski, 2006. Optimal Synthesis of Multiple Output Boolean Functions Using a Set of Quantum Gates by Symbolic Reachability Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1652-1663.
  • H Thapliyal and N Ranganathan, 2009. Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 229-234.
  • H R Bhagyalakshmi and M K Venkatesha, 2010. An Improved Design of a Multiplier using Reversible Logic Gates. International Journal of Engineering Science and Technology, vol. 2(8), pp. 3838-3845.
  • Rigui Zhou, Yang Shi, Jian Cao and Huian Wang, 2010. Comment on Design of a Novel Reversible Multiplier Circuit using HNG Gate in Nanotechnology. World Applied Sciences Journal, vol. 10(2), pp. 161-165.
  • M S Islam, M M Rahman, Z Begum and M Z Hafiz, 2009. Low Cost Quantum Realization of Reversible Multiplier Circuit. Information Technology Journal, vol. 8(2), pp. 208-213.
  • H Thapliyal and M B Srinivas, 2006. Novel Reversible Multiplier Architecture using Reversible TSG gate. IEEE International Conference on Computer Systems and Applications, pp. 110-103.
  • Majid Haghparast, Magid Mohammade, Keivan Navi and Mohammad Eshghi, 2009. Optimized Reversible Multiplier Circuit. Journal of Circuits, Systems and Computers, vol. 18(2), pp. 311-321.
  • Noor Muhammed Nayeem, Lafifa Jamal and Hafiz Md Hasan Babu, 2009. Efficient Reversible Montgomery Multiplier and its Application to Hardware Cryptography. Journal of Computer Science, vol. 5(1), pp. 49-56.
  • Maryam Eshanpour, Payman Moallem and Abbas Vafaei, 2010. Design of a Novel Reversible Multiplier Circuit using Modified Full Adder. IEEE International Conference on Computer Design and Applications, vol. 3, pp. 230-234.
  • Sebastian Offermann, Robert Wille, Gerhard W Dueck and Rolf Drechsler, 2010. Synthesizing Multiplier in Reversible Logic. Thirteenth IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 335-340.
  • Fateme Naderpour and Abbas Vafaei, 2008. Reversible Multipliers: Decreasing the depth of the Circuit. Fifth IEEE International Conference on Electrical and Computer Engineering, pp. 306-310.
  • Anindita Banerjee and Anirban Pathak, 2010. Reversible Multiplier Circuit. Third IEEE International Conference on Emerging Trends in Engineering and Technology, pp. 781-786.
  • Nidhi Syal and H P Sinha, 2011. High Performance Reversible Parallel Multiplier. International Journal of VLSI and Signal Processing Application, vol. 1, issue 3, pp. 21-26.
  • H Thapliyal and N Ranganathan, 2011. A New Reversible Design of BCD Adders. IEEE Conference and Exhibition on Design, Automation and Test in Europe, pp. 1- 4.
  • H Thapliyal and N Ranganathan, 2011. A New Design of the Reversible Subtractor Circuit. Eleventh IEEE Conference on Nanotechnology, pp. 1430-1435.
  • Michael Nachtigal, H Thapliyal and N Ranganathan, 2011. Design of a Reversible Floating-point Adder Architecture. Eleventh IEEE Conference on Nanotechnology, pp. 451- 456.
  • Haghparast, Somayyeh Jafarali Jassbi, Keivan Nvi and Omid Hashemipour, 2008. Design of a Noval Reversible Multiplier Circuit using HNG Gate in Nanotechnology. World Applied Sciences Journal, vol. 3, issue 6, pp. 974-978.