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Efficient Router Architecture design on FPGA for Torus based Network on Chip

International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 55 - Number 14
Year of Publication: 2012
Saraswathi Venugopal
Arokiasamy Arulanandasamy
R. Ramachandran

Saraswathi Venugopal, Arokiasamy Arulanandasamy and R Ramachandran. Article: Efficient Router Architecture design on FPGA for Torus based Network on Chip. International Journal of Computer Applications 55(14):30-35, October 2012. Full text available. BibTeX

	author = {Saraswathi Venugopal and Arokiasamy Arulanandasamy and R. Ramachandran},
	title = {Article: Efficient Router Architecture design on FPGA for Torus based Network on Chip},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {55},
	number = {14},
	pages = {30-35},
	month = {October},
	note = {Full text available}


Network-on-Chip (NoC) is an emerging technology for interconnecting multiple cores on a single silicon chip. In NoCs, hardware modules such as CPU cores, memories and I/O controllers are interconnected through a suitable network topology for sharing the data. This paper proposes a Multiprocessor NoC (MPNOC) based on torus network topology using wormhole switching. This NoC architecture consists of heterogeneous processing elements and core interfacing devices. We show that the proposed novel router architecture composed of small crossbar switch with Virtual channel memory requires less logical resources and reduce the routing complexity in wormhole switching in torus which provide high throughput performance evaluation and FPGA implementation of the system results are also given.


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