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Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 57 - Number 11
Year of Publication: 2012
Authors:
Rajesh Mehra
Swapna Devi
S. S. Pattnaik
10.5120/9161-3318

Rajesh Mehra, Swapna Devi and S S Pattnaik. Article: Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization. International Journal of Computer Applications 57(11):41-47, November 2012. Full text available. BibTeX

@article{key:article,
	author = {Rajesh Mehra and Swapna Devi and S. S. Pattnaik},
	title = {Article: Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {57},
	number = {11},
	pages = {41-47},
	month = {November},
	note = {Full text available}
}

Abstract

In this paper a hybrid approach is presented to design and implement a GSM digital down convertor for enhanced resource utilization. The proposed DDC has been implemented by hybridizing the multiplier less and multiplier based decimators. A multiplier less CIC decimator has been used to reduce the cost by reducing the multiplier requirement. Two computationally efficient equiripple polyphase decomposition structure based decimators have been to reduce the filter order and hardware complexity. The embedded multipliers, LUTs and BRAMs have been efficiently utilized to enhance the system performance and resource utilization. The proposed GSM DDC has been designed and simulated Matlab and Simulink, synthesized with Xilinx Synthesis Tool and implemented on Virtex-II Pro based xc2vp20 FPGA device. The proposed design has shown a minimum period of 159. 96 MHz with enhance resource utilization ranging from 4-12 % in terms slices, flip flops LUTs, BRAMs and multipliers.

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