The week's pick
Random Articles
Reseach Article
FPGA based Implementation of High Speed Double Precision Floating Point Multiplier with Tiling Technique using Verilog
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 58 - Number 21 |
| Year of Publication: 2012 |
| Authors: Addanki Purna Ramesh, A. V. N. Tilak, A. M. Prasad |
10.5120/9407-3814
|
Addanki Purna Ramesh, A. V. N. Tilak, A. M. Prasad . FPGA based Implementation of High Speed Double Precision Floating Point Multiplier with Tiling Technique using Verilog. International Journal of Computer Applications. 58, 21 ( November 2012), 17-25. DOI=10.5120/9407-3814
Abstract
Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. For many signal processing, and graphics applications, it is acceptable to trade off some accuracy (in the least significant bit positions) for faster and better implementations. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this paper we describe an implementation of high speed IEEE 754 double precision floating point multiplier using tiling technique and targeted for Xilinx Virtex-6 Field Programmable Gate Array. Verilog is used to implement the design. The design achieved 436.815 MFlops with latency of seven clock cycles which is 97% fast compared to Xilinx floating point multiplier core. It handles the overflow, underflow cases and truncation rounding mode.
References
- B. Fagin and C. Renard, “Field Programmable Gate Arrays and Floating Point Arithmetic”, IEEE Transactions on VLSI, vol. 2, no. 3, pp. 365–367, 1994.
- N. Shirazi, A. Walters, and P.Athanas, “Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines”, Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM‟95), pp.155–162, 1995.
- L. Louca, T. A. Cook, and W.H. Johnson,“Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs” , Proc. of the 83rd IEEE Symposium on FPGAs for Custom Computing Machines (FCCM‟96), pp. 107–116, 1996.
- B. Lee and N. Burgess, “Parameterisable Floating-point Operations on FPGA”, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems, and Computers, 2002
- Sebastian Banescu,Florent de Dinechin, Bogdan Pasca “Multipliers for Floating-point Double Precision and Beyond on FPGAs”, Proc. of First International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2010),Tsukuba, Ibaraki, Japan, June 1, 2010.
- M.Al-Ashrafy, A.Salem and W.Anis, “An Efficient Implementation of Floating Point Multiplier”, Proc. of Electronics Communications and Photonics Conference (SIECPC) 2011, Saudi International, pp.1-5, 2011.
Index Terms
Keywords