FIFO is implies first in first out using queue methodology for memories read and write of any information and data using some control logic. The whole work of FIFO is fully dependent on the control circuitry and clock domain. It is often used to control the flow of data from source to destination by the transition of every clock. Basically FIFO differentiate by clock domain either Synchronous or Asynchronous. There are various methods to designing and synthesized FIFO but here fully focused on the memory which is used to store the data in domain of clock either sync. and async. or single and multiple clock cycles. This paper will differentiate the design, synthesize and analyze a Synchronous FIFO using Register file memory by older version of Synchronous FIFO. In this paper, conclude the effect of using register file instead of random access memory for storage of data in FIFO memory. This work shows change the parameters like on-chip components (clock, signal, input and outputs etc), clock domain, type of resources, and how to minimize and optimize hierarchy of the device. The RTL description for the FIFO is written using Verilog HDL (hardware description language). And design is simulated and synthesizes in Xilinx ISE Design suit 12. 4. The RTL code simulated in ISim Simulator.

Verilog FIFO RTL fifo_full fifo_empty sync. fifo async. Fifo RAM Register file read write