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Design of Efficient Complementary Pass Transistor based Modified Booth Encoder Array Multiplier
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 64 - Number 5 |
| Year of Publication: 2013 |
| Authors: Sajan P. Philip, S. P. Prakash, S. Valarmathi |
10.5120/10631-5363
|
Sajan P. Philip, S. P. Prakash, S. Valarmathi . Design of Efficient Complementary Pass Transistor based Modified Booth Encoder Array Multiplier. International Journal of Computer Applications. 64, 5 ( February 2013), 25-31. DOI=10.5120/10631-5363
Abstract
In this paper a method to build a faster array multiplier based on Radix 4 Modified Booth Encoder - which is broadly used for the signed multiplication applications- with less area and power is presented. This is achieved by optimizing the overall interconnection delay in the partial product array and by scheming the most efficient Full Adder and Booth Encoder in Complementary Pass Transistor Logic approach. The proposed array multiplier's performance in terms of delay, power and area is compared with conventional as well as Baugh-Wooley Multiplier. In order to optimize the power and area of the multiplier, a CPL Based MBE with standard partial product array is proposed and designed in full custom style. The use of efficient 10 Transistor based Full adders based on CPL logic ensures that the entire design is in CPL logic, which provides a regular outline with less interconnection intricacy.
References
- A. D. Booth,"A signed binary multiplication technique," Quarterly Journal of Mechanics and Applied Mathematics, vol. 2, pp. 236-240, 1951.
- O. L. MacSorley, "High-speed arithmetic on binary computers," IRE Transaction on Electronic Computers, vol. 49, pp. 67-91, 1961.
- A. R. Cooper, "Parallel Architecture Modified Booth Multiplier", Proceedings of the Institution of Electrical Engineers, 1989.
- J. Fadavi-Ardekani, "M × N booth encoded multiplier generator using optimized Wallace trees," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 1, no. 2, pp. 120–125, Jun, 1993.
- W. -C. Yeh and C. -W. Jen, "High-speed booth encoded parallel multiplier design," IEEE Trans. Comput. , vol. 49, no. 7, pp. 692–701, Jul, 2000.
- Ayman A. Fayed, Magdy A. Bayoumi, "A Novel Architecture for Low-Power Design of Parallel Multipliers," vlsi,pp. 0149, IEEE Computer Society Workshop on VLSI 2001.
- Razaidi Hussin, Ali Yeon Md. Shakaff, Norina Idris1, Zaliman Sauli1, Rizalafande Che Ismail1 and Afzan Kama An Efficient Modified Booth Multiplier Architecture, International Conference on Electronic Design, 2008.
- Shiann-Rong Kuang and Jiun-Ping Wang "Modified Booth Multipliers with a Regular Partial Product Array" IEEE Transactions on Circuits and Systems—II Volume. 56, No. 5, 2009.
- Soojin Kim and Kyeongsoon Cho, "Design of High-speed Modified Booth Multipliers Operating at GHz Ranges," World Academy of Science, Engineering and Technology, Vol. 7, No. 2, 2010.
- S. K. Sahoo and C. Shekhar, "A fast final adder for a 54-bit parallel multiplier for DSP application",international journal of electronics, vol. 98, no. 12, pp. 1625-1638, 2011.
- S. K. Sahoo and C. Shekhar,"Delay Optimized Array Multiplier for Signal and Image Processing", 2011 International Conference on Image Information Processing, 2011.
- C. Senthilpari "A low power and High performance Radix-4 Multiplier design using a Modified Pass Transistor Logic Technique" IETE Journel of Research Vol. 57, Issue 2, 2012.
- Neil. H. Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design," Addison-Wesley, ISBN 0201733897,pp 361-380, 1993.
- Kiat-Seng Yeo and Kaushik Roy, "Low-Voltage,Low-Power VLSI Subsystems" Tata McGraw-Hill,ISBN-13-978-0-07-067750-0, pp 119- 146, 2009.
- K . Roy and S. C. Prasad, "Low Power CMOS VLSI Circuit Design," Wiley, 2009.
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