Call for Paper - March 2023 Edition
IJCA solicits original research papers for the March 2023 Edition. Last date of manuscript submission is February 20, 2023. Read More

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 68 - Number 5
Year of Publication: 2013
Arun Kumar Sunaniya
Kavita Khare

Arun Kumar Sunaniya and Kavita Khare. Article: Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications. International Journal of Computer Applications 68(5):26-33, April 2013. Full text available. BibTeX

	author = {Arun Kumar Sunaniya and Kavita Khare},
	title = {Article: Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {68},
	number = {5},
	pages = {26-33},
	month = {April},
	note = {Full text available}


The Analog to Digital converters (ADC) play a very important role in today's world of electronic systems. The requirement of present applications demands high speed, low power dissipation, minimum area, low noise and application specific resolution. Out of the various types of ADCs available the flash ADC is most popular for its highest conversion rate and its wide applications. On the down side the flash ADC dissipates high power due to the presence of resistance ladder. The power dissipation further increases with increase in resolution. In this research two different approaches are presented which eliminates the resistor ladder completely and hence reduce the power demand drastically. The first approach is Switched Inverter Scheme (SIS) ADC; it is realized for 3 bits using 7 comparator circuits of varying size in CMOS 45nm technology with Predictive Technology Model (PTM). The test result obtained indicates an offset error of 0. 014 LSB. The full scale error is of -0. 112LSB. The gain error is of 0. 07 LSB, actual full scale range of 0. 49V, worst case DNL & INL each of -0. 3V. The power dissipation for the SIS ADC is 207. 987 µwatts; Power delay product (PDP) is 415. 9 fWs, and the area overhead is 1. 89µm2. The second approach is Sleep transistor SIS ADC. This approach shows 71% improvement in power dissipation. Whereas PDP is found to be 107. 3 fWs and area overhead is 1. 94 µm2 for Sleep transistor SIS ADC.


  • Amol Inamdar, Anubhav Sahu, Jie Ren, Aniruddha Dayalu, and Deepnarayan Gupta, "Flash ADC Comparators and Techniques for their Evaluation", IEEE Transactions on Applied Superconductivity, Vol. 23, no. 3, ISSN No. 1051-8223,pp. 1-8, Jan 2013.
  • Xiangliang Jin, Zhibi Liu, and Jun Yang, "New Flash ADC Scheme With Maximal 13 Bit Variable Resolution and Reduced Clipped Noise for High-Performance Imaging Sensor", IEEE Sensors Journal, Vol. 13, no. 1, pp. 167-171, Jan. 2013.
  • Young-Kyun Cho, Jae-Ho Jung, and Kwang Chun Lee, "A 9-bit 100-MS/s Flash-SAR ADC without Track-and-Hold Circuits", International Symposium on Wireless Communication Systems (ISWCS),ISBN No. 978-1-4673-0761-1, pp. 880-884, Aug 2012.
  • Joyjit Mukhopadhyay and Soumya Pandit, " Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics", Hindawi Publishing Corporation VLSI Design, Vol. 2012, pp. 1-13,2012.
  • Chakir Mostafa,Hassan Qjidaa, "1 GS/s, Low Power FlashAnalog to Digital Converter in 90nm CMOSTechnology", IEEE conference on Multimedia Computing and Systems (ICMCS), 2012 International ,pp. 1097 – 1100,May2012.
  • Yun-Shiang Shu, "A 6b 3GS/s 11mW Fully Dynamic Flash ADC in 40nm CMOS with Reduced Number of Comparators", IEEE Symposium on VLSI Circuits Digest of Technical Papers ,pp. 26-27, June2012.
  • Ch. Vassou, L. Mountrichas, S. Siskos, "A NMOS Bulk Voltage Trimming Offset Calibration Technique for a 6-bit 5GS/s Flash ADC", IEEE International Conference on Instrumentation and Measurement Technology (I2MTC),pp. 5-8,May 2012.
  • Soon-Kyun Shin, Jacques C. Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, and Matthew Z. Straayer, "A 12b 200MS/s Frequency Scalable Zero-Crossing Based Pipelined ADC in 55nm CMOS" ,IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4,2012.
  • Yuji Gendai, and Akira Matsuzawa, "A Speci?c Distortion Pattern of Flash ADCs Identi?ed by Discriminating Time-Domain Analysis", IEEE transactions on instrumentation and measurement, vol. 61, no. 2, pp. 316-325, Feb. 2012.
  • Amir Zjajo Jose, Pineda de Gyvez "Low-Power High Resolution Analog to Digital Converters, Design Test and Calibration" ISBN 978-90-481-9724-8, First edition, Springer, 2011.
  • Dharmendra Mani Varma "Reduced Comparator Low power Flash ADC using 35nm CMOS", IEEE Conference on Electronics Computer Technology (ICECT) ,pp. 385- 388, April 2011.
  • Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto Sangiovanni Vincentelli, Jan Craninckx, Geert Van der Plas, "A 6-Bit 50-MS/s Threshold Con?guring SAR ADC in 90-nm Digital CMOS",IEEE Trans. On Circuits And Systems-I,Vol. 58, no. 12, December 2011.
  • Sudakar S. Chauhan, S. Manabala, S. C. Bose and R. Chandel, "A New Approach To Design Low Power CMOS Flash A/D Converter", International Journal of VLSI design & Communication Systems(VLSICS),Vol. 2,no. 2,pp. 10-108,June 2011.
  • A. Ávila, D. Espejo, "A SPICE-compatible Model for Intel's 45nm High K MOSFET", The World Congress on Engineering and Computer Science (WCECS) Proceedings, ISBN no. 978-988-19251-7-6, Vol. 2, pp. 762-765, October 2011.
  • G. Torfs, Z. Li, J. Bauwelinck, X. Yin, G. Van der Plas and J. Vandewege, "Low-power 4-bit ?ash analogue to digital converter for ranging applications", IEEE Electronics Letters, Vol. 47 no. 1, Jan. 2011.
  • T. Esther Rani, Dr. Rameshwar rao, "Area And Power Optimized Multipliers With Minimum Leakage", IEEE International Conference on Electronic Computer Technology - ICECT , ISBN no. 978-1-4244-8679,pp. 284 -287, Nov. 2011.
  • Oktay Aytar and Ali Tangel, "Employing threshold inverter quantization (TIQ) technique in designing 9-Bit folding and interpolation CMOS analog-to-digital converters (ADC)", Scientific Research and Essays,Vol. 6,no. 2, ISSN no. 1992-2248, pp. 351-362,January 2011.
  • Hiroshi Fuketa, SatoshiIida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai, "A Closed-form Expression for Estimating Minimum Operating Voltage (VDDmin) of CMOS Logic Gates", IEEE Conference on Design Automation (DAC),ISBN no. 978-1-4503-0636-2, pp. 984-989, June 2011.
  • Baozeng Guo, Tao Ma, Yubo Zhang "Design of A Novel Domino XNOR Gate for 32-nm node CMOS Technology", IEEE International conference on Electric Information and Control Engineering (ICEICE), ISBN no. 978-1-4244-8036-4, pp. 289-292 April 2011.
  • Tomoyuki Yamase, Hiroaki Uchida, and Hidemi Noguchi ,"A 22-mW 7b 1. 3-GS/s Pipeline ADC with 1-bit/stage Folding Converter Architecture", Symposium on VLSI Circuits Digest of Technical Papers, ISBN no. 978-4-86348-1657, pp. 124-125,2011.
  • Jaeyoon Kim, Sandip Tiwari, "Inexact Computing for Ultra Low Power Nanometer Digital Circuit Design", IEEE/ACM International Symposium on Nanoscale Architectures, 978-1-4577-0995-1, pp. 24-31, Jan 2011.
  • Tsung-Ching Huang, Kenjiro Fukuda, Chun-Ming Lo, Yung-Hui Yeh, Tsuyoshi Sekitani, Takao Someya and Kwang-Ting Cheng, "Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics" IEEE Transactions on Electron Devices, Vol. 58, no. 1, pp. 141-150, Jan. 2011.
  • Arun Kumar Sunaniya, Kavita Khare, "A Design Comparison of Low Power 50 nm Technology Based Inverter with Sleep Transistor and MTCMOS Scheme", International Journal of Engineering Science and Technology (IJEST), Vol. 3 No. 10, ISSN no. 0975-5462,pp. 7744-7753, October 2011.
  • Arun Kumar Sunaniya, Kavita Khare, "A Low power 50 nm Technology Based CMOS Inverter with Sleep Transistor Scheme" International Journal of Computer Science Engineering & Technology (IJCSET) Vol. 1 No. 9, ISSN no. 2231-0711,pp. 560-562, October 2011.
  • The "International Technology Road map of semiconductor" ITRS, pp 61-66, 2010.
  • Meghana Kulkarni, V. Sridhar, G. H. Kulkarni,"4-Bit Flash Analog to Digital Converter Design using CMOS-LTE Comparator", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ,ISBN no. 978-1-4244-7456-1, pp. 772-775, Oct. 2010.
  • De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, and Shih-Chieh, "Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation", IEEE transactions on computer-aided design of integrated circuits and systems, vol. 29, no. 8,pp. 1285-1290, August 2010.
  • Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, and Jong-Kee Kwon, "A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique" IEEE Circuits And Systems, ISSN: 1549-7747 pp 502-506 Vol. 57, Issue:7 , July 2010.
  • R. Jacob Baker "CMOS: Mixed Signal Circuit Design", Second Edition, Wiley-IEEE Press, ISBN 978 0470-29026-2, 2009.
  • A. B. Bhattacharyya "Compact MOSFET Models For VLSI Design" John Wiley & Sons, ISBN: 978-0-470-82342-2, 2009.
  • P. Iyappan, P. Jamuna and S. Vijayasamundiswary, "Design of Analog to Digital Converter Using CMOS Logic", IEEE International Conference on Advances in Recent Technologies in Communication and Computing, ISBN no. 978-0-7695-3845-7, pp. 74-76, 2009.
  • Rajashekar G, M S Bhat "Design of Resolution Adaptive TIQ Flash ADC using AMS 0. 35µm Technology" IEE International Conference on Electronic Design (ICED), ISSN 978-1-4244-2315-6, pp. 1-6, Dec-2008.
  • O. Aytar, A. Tangel, G. Dundar, "A 9-Bit 1GS/S CMOS Folding ADC Implementation Using TIQ Based Flsh ADC Cores" MIXDES 15th Int. Conference 2008, Print ISBN: 978-83-922632-7-2 Poznan, Poland, pp 159-164, Oct-2008.
  • Erik Sall and Mark Vesterbacka, "Thermometer-to-Binary Decoders for Flash Analog-to-Digital Converters", European Conference on Circuit Theory and Design - ECCTD,ISBN no. 1-4244-1342-7, pp. 240-243, July2007.
  • Mingzhen Wang, Chien-In Henry Chen, and Shailesh Radhakrishnan,"Low-Power 4-b 2. 5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS", IEEE Transactions on Instrumentation and Measurement, Vol. 56, no. 3, pp. 1064- 1073, June 2007.
  • Kaijian Shi David Howard , "Challenges in Sleep Transistor Design and Implementation in Low-Power Designs",pp. 113-116,July 2006.
  • Ferragina, V. ; Ghittori, N. ; Maloberti, F. , "Low-power 6-bit flash ADC for high-speed data converters architectures", IEEE International Symposium on circuits and Systems (ISCAS), Print ISBN: 0-7803-9389-9, pp. 3930-3933, Sep- 2006.
  • Jincheol Yoo,Kyusun Choi and Jahan Ghaznavi, "A A0. 07µm CMOS Flash Analog-to-Digital Converter for High Speed and Low Voltage Applications", GLSVLSI, pp. 56-59,2003.
  • Xuemei (Jane) Xi, Mohan Dunga, Jin He, Weidong Liu, Kanyu M. Cao, Xiaodong Jin, Jeff Jou, Mansun Chan, Ali M. Niknejad, Chenming Hu "BSIM4. 3. 0 MOSFET Model: User Manual", 2003.
  • P. E. Allen and D. R. Holberg. "CMOS Analog Circuit Design" second edition oxford university press. ISBN 019 5116 445, 2002.
  • D. Lee, J. Yoo, and K. Choi. "Design Method and Automation of Comparator Generation for Flash A/D Converters". IEEE International Symposium on Quality Electronic Design, pp. 138-142, 2002.
  • D. Lee, J. Yoo, K. Choi, and J. Ghaznavi. "Fat Tree Encoder Design for Ultra-High Speed Flash A/D Converters", IEEE Midwest Symposium on Circuits and Systems, 2002.