CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Article:Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits

by Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 7 - Number 5
Year of Publication: 2010
Authors: Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande
10.5120/1162-1467

Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande . Article:Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits. International Journal of Computer Applications. 7, 5 ( September 2010), 1-4. DOI=10.5120/1162-1467

@article{ 10.5120/1162-1467,
author = { Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande },
title = { Article:Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits },
journal = { International Journal of Computer Applications },
issue_date = { September 2010 },
volume = { 7 },
number = { 5 },
month = { September },
year = { 2010 },
issn = { 0975-8887 },
pages = { 1-4 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume7/number5/1162-1467/ },
doi = { 10.5120/1162-1467 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T19:55:34.149918+05:30
%A Dhananjay E. Upasani
%A Sandip B. Shrote
%A Pallavi S.Deshpande
%T Article:Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 7
%N 5
%P 1-4
%D 2010
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Most of the portable systems, such as cellular communication devices, and laptop computers operate from a limited power supply. Devices like cell phones have long idle times and operate in standby mode when not in use. Consequently, the extension of battery-based operation time is a significant design goal which can be made possible by controlling the leakage current flowing through the CMOS gate. This article reviews the off-state leakage mechanisms like weak inversion leakage, gate induced drain leakage and channel punchthrough current. Various circuit level techniques to reduce standby leakage and their design trade-off are discussed. Based on the surveyed techniques, a designer would be able to select the appropriate leakage optimization technique for a standby mode.

References
  1. K. Roy, S. Mukhopadhyay and H.Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” In the Proceedings of the IEEE, vol. 91, no. 2, pp. 305–327,
  2. M.Jamal Dean, “DIBL in Short Channel NMOS Devices”, IEEE Transaction on Electron Devices, Vol39, No4, 908- 915, 1992
  3. Farzan Fallah and Massoud Pedram, “Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits”, IEICE transactions on electronics, vol. 88, no.4, pp. 509-519, 2005
  4. Y. Ye et al. IEEE Symposium on VLSI Circuits, 1998.
  5. S. Mukhopadhyay,IEEE Transactions on VLSI Systems, 2003.
  6. S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. P. Chandrakasan, “Scaling of stack effect and its application for leakage reduction,” Proc. IEEE ISLPLED, pp. 195– 200, Aug. 2001.
  7. N. Hanchate and N.Ranganathan, “LECTOR: A Technique for Leakage Reduction in CMOS Circuits”, IEEE Transactions on VLSI Systems,vol. 12, pp. 196-205, Feb.,2004.
  8. Srikanth Katrue and Dhireesha Kudithipudi, “GALEOR: Leakage Reduction for CMOS Circuits”, 15th IEEE International Conference on Electronics, Circuits and Systems, 2008, Volume, Issue, Aug. 31 2008-Sept. 3 2008 Page(s):574 - 577
  9. Kao J., Chandrakasan A. and Antoniadis D., “Transistor sizing issues and tool for multi-threshold CMOS technology,” in Proc. ACM/IEEE Design Automation Conf., pp. 495–500, 1997.
  10. Kao, J. T., and Chandrakasan, A. P. “Dual-Threshold Voltage Techniques for Low-power Digital Circuits”, IEEE Journal of Solid-State Circuits 35, pp.1009-1018, 7 (July 2000).
  11. Ken Choi and Jerry Frenkil, “An Analysis Methodology for Dynamic Power Gating”, Sequence Design Inc, pp. 1- 13, 26 (July 2007).
  12. J. Kao, A. Chandrakasan, and D. Antoniadis,“Transistor sizing issues and tool for multi-threshold CMOS technology,” in Proc. 34th DAC, 1997, pp. 409–414.
  13. C. Gopalakrishnan and S. Katkoori, “Resource allocation and binding approach for low leakage power,” in Proc. IEEE Int. Conf. VLSI Design,Jan. 2003, pp. 297–302.
  14. T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, “Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 409–412, May 2000.
  15. M. R. Stan, “Low threshold CMOS circuits with low standby current,” in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), pp. 97–99, Aug. 1998.
  16. H. Kawaguchi, K. Nose, and T. Sakurai, “A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 192–193, Feb. 1998.
  17. Alexandre Valentian and Edith Beigne, “Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability”, IEEE J. OF Solid-State Circuits, vol. 43, no. 7, July 2008.
  18. Kyung Ki Kim; Yong-Bin Ki, “Optimal Body Biasing for Minimum Leakage Power in Standby Mode”, IEEE International Symposium on Circuits and Systems, 27-30 May 2007, Page(s):1161 - 1164
Index Terms

Computer Science
Information Sciences

Keywords

Standby leakage LECTOR GALEOR

Powered by PhDFocusTM