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Modeling and Simulation of 2D Mesh Topological Network on Chip (NOC)

by Prachi Agarwal, Anil Kumar Sharma, Adesh Kumar
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 72 - Number 21
Year of Publication: 2013
Authors: Prachi Agarwal, Anil Kumar Sharma, Adesh Kumar
10.5120/12667-9297

Prachi Agarwal, Anil Kumar Sharma, Adesh Kumar . Modeling and Simulation of 2D Mesh Topological Network on Chip (NOC). International Journal of Computer Applications. 72, 21 ( June 2013), 25-31. DOI=10.5120/12667-9297

@article{ 10.5120/12667-9297,
author = { Prachi Agarwal, Anil Kumar Sharma, Adesh Kumar },
title = { Modeling and Simulation of 2D Mesh Topological Network on Chip (NOC) },
journal = { International Journal of Computer Applications },
issue_date = { June 2013 },
volume = { 72 },
number = { 21 },
month = { June },
year = { 2013 },
issn = { 0975-8887 },
pages = { 25-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume72/number21/12667-9297/ },
doi = { 10.5120/12667-9297 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:38:32.401798+05:30
%A Prachi Agarwal
%A Anil Kumar Sharma
%A Adesh Kumar
%T Modeling and Simulation of 2D Mesh Topological Network on Chip (NOC)
%J International Journal of Computer Applications
%@ 0975-8887
%V 72
%N 21
%P 25-31
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Network on chip (NOC) architecture is an approach to develop large and complex systems on a single chip. In this work, 2D mesh topological structure has been implemented in Very High Speed Integrated Circuit Hardware Description Language (VHDL). The architecture supports physical and architectural level design integration. Basic communication mechanism between resources is envisioned to be packet switched message passing through the switches. Node identification is done based on addresses of nodes located at X and Y axis. Network configuration is chosen for cluster 8 x 8 and 16 x 16 which signifies that 64 nodes and 256 nodes are available to communicate each other which are aligned in crossbar structure. Design was implemented in Xilinx 14. 2 VHDL software, and functional simulation was carried out in Modelsim 10. 1 b, student edition

References
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Index Terms

Computer Science
Information Sciences

Keywords

Field Programmable Gate Array (FPGA). Network on chip (NOC) Very High Speed Integrated Circuit hardware Description language (VHDL

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