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Novel Architecture of High Speed Parallel MAC using Carry Select Adder

by Deepika Setia, Charu Madhu
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 74 - Number 1
Year of Publication: 2013
Authors: Deepika Setia, Charu Madhu
10.5120/12851-9334

Deepika Setia, Charu Madhu . Novel Architecture of High Speed Parallel MAC using Carry Select Adder. International Journal of Computer Applications. 74, 1 ( July 2013), 32-38. DOI=10.5120/12851-9334

@article{ 10.5120/12851-9334,
author = { Deepika Setia, Charu Madhu },
title = { Novel Architecture of High Speed Parallel MAC using Carry Select Adder },
journal = { International Journal of Computer Applications },
issue_date = { July 2013 },
volume = { 74 },
number = { 1 },
month = { July },
year = { 2013 },
issn = { 0975-8887 },
pages = { 32-38 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume74/number1/12851-9334/ },
doi = { 10.5120/12851-9334 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:41:05.935969+05:30
%A Deepika Setia
%A Charu Madhu
%T Novel Architecture of High Speed Parallel MAC using Carry Select Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 74
%N 1
%P 32-38
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, new hardware architecture of multiplier and accumulator (MAC) for high speed arithmetic was designed. The performance was improved by merging multiplication with accumulation and organize a hybrid type carry save adder (CSA). The proposed CSA tree uses 1's complement based radix-4 and radix-8 modified booth algorithm(MBA). The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to reduce the number of the input bits of the final adder. This MAC add the intermediate results in the form of sum and carry bits instead of the final adder output, which made it possible to optimize the pipeline system to improve the performance. The final addition was carried out by high speed carry select adder (CSLA) with binary to excess convertor using CLA. Based on the theoretical and experimental estimation, we analyzed the results in terms of delay. The design is implemented using VHDL language and simulated using Xilinx ISE10. 1 Simulator.

References
  1. J. J. F. Cavanagh, Digital Computer Arithmetic. New York: McGraw-Hill, 1984.
  2. O. L. MacSorley, "High speed arithmetic in binary computers," Proc. IRE, vol. 49, pp. 67-91, Jan. 1961.
  3. A. D. Booth, "A signed binary multiplication technique," Quart. J. Math. , vol. IV, pp. 236–240, 1952.
  4. C. S. Wallace, "A suggestion for a fast multiplier," IEEE Trans. Electron Comput. , vol. EC-13, no. 1, pp. 14–17, Feb. 1964
  5. A. R. Cooper, "Parallel architecture modified Booth multiplier," Proc. Inst. Electr. Eng. G, vol. 135, pp. 125–128, 1988 8968190248.
  6. N. R. Shanbag and P. Juneja, "Parallel implementation of a 4x4-bit multiplier using modified Booth's algorithm," IEEE J. Solid-State Circuits,vol. 23, no. 4, pp. 1010–1013, Aug. 1988.
  7. A. R. Cooper, "Parallel architecture modified Booth multiplier," Proc. Inst. Electr. Eng. G, vol. 135, pp. 125–128, 1988.
  8. N. R. Shanbag and P. Juneja, "Parallel implementation of a 4??4-bit multiplier using modified Booth's algorithm," IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 1010–1013, Aug. 1988.
  9. G. Goto, T. Sato, M. Nakajima, and T. Sukemura, "A 54??54 regular structured tree multiplier," IEEE J. Solid-State Circuits, vol. 27, no. 9,pp. 1229–1236, Sep. 1992.
  10. J. Fadavi-Ardekani, "M??N Booth encoded multiplier generator using optimized Wallace trees," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 1, no. 2, pp. 120–125, Jun. 1993.
  11. F. Elguibaly and A. Rayhan, "Overflow handling in inner-product processors,"in Proc. IEEE Pacific Rim Conf. Commun. , Comput. , Signal Process. , Aug. 1997, pp. 117–120.
  12. F. Elguibaly, "A fast parallel multiplier–accumulator using the modified Booth algorithm," IEEE Trans. Circuits Syst. , vol. 27, no. 9, pp. 902–908, Sep. 2000.
  13. Samiappa,Sakthikumaran,S. Salivahanan, V. S. Kanchana Bhaaskaran, V. Kavinilavu, B. Brindha and CVinoth, "A Very Fast and Low Power Carry Select Adder Circuit",978-1-4244-8679-3/11. 2011 IEEE.
  14. P. Devi and A. Girdher, "Improved Carry Select Adder with Reduced Area and Low Power Consumption", International Journal of Computer Applications (0975– 8887) vol. 3 – No. 4, June, 2010. .
  15. Raahemifar, K. and Ahmadi, M. , "Fast carry look ahead adder", IEEE Canadian Conference on Electrical and Computer Engineering, 1999.
  16. Taewhan Kim and Junhyung Um,"A Practical Approach to the Synthesis of Arithmetic Circuits Using Carry-Save-Adders" IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 5, MAY 2000.
  17. Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase," A 64bit Carry Look-ahead CMOS Adder using Modified Carry Select" IEEE 1995 CUSTOM INTEGRATED CIRCUITS CONFERENCE.
  18. A. Abdelgawad , Magdy Bayoumi "High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Processing Applications"IEEE 2007.
  19. Shanthala S, Cyril Prasanna Raj, Dr. S. Y. Kulkarni, "Design and VLSI Implementation of Pipelined Multiply Accumulate Unit", IEEE computer society, 2009
  20. P. Zicari, S. Perri, P. Corsonello, and G. Cocorullo, "An optimized adder accumulator for high speed MACs," Proc. ASICON 2005, vol. 2, pp. 757–760, 2005.
  21. K. Babulu et al, G. Parasuram "FPGA Realization of Radix-4 Booth Multiplication Algorithm for High Speed Arithmetic Logics", (IJCSIT) Vol. 2 (5) , 2011, 2102-2107.
  22. Young-Ho Seo, Dong-Wook Kim, ''A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2Modified Booth Algorithm'' IEEE transactions on very large scale integration (VLSI) systems, vol. 18, no. 2, February2010.
  23. G. A. Ruiz1 and Mercedes Granda,"Efficient hardware implementation of 3X for radix-8 encoding", Proc. of SPIE Vol. 6590 65901I-1
Index Terms

Computer Science
Information Sciences

Keywords

Modified Booth algorithm (MBA) Multiplier and Accumulate (MAC) Carry Look Ahead Adder(CLA) Carry Select adder(CSLA)

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