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Design of Efficient Reversible Fault tolerant Adder/Subtractor

International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 74 - Number 9
Year of Publication: 2013
Prashanth. N. G
Savitha. A. P
M. B. Anandaraju
Naveen. K. B

Prashanth. N G, Savitha. A P, M B Anandaraju and Naveen. K B. Article: Design of Efficient Reversible Fault tolerant Adder/Subtractor. International Journal of Computer Applications 74(9):23-28, July 2013. Full text available. BibTeX

	author = {Prashanth. N. G and Savitha. A. P and M. B. Anandaraju and Naveen. K. B},
	title = {Article: Design of Efficient Reversible Fault tolerant Adder/Subtractor},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {74},
	number = {9},
	pages = {23-28},
	month = {July},
	note = {Full text available}


In recent years, reversible logic is the most popular and emerging technology and it will be having wide applications in the field of Low power CMOS, quantum computing and optical computing. Circuits with reversible logic gates provide low power dissipation and low energy loss. This paper proposes the Adder/Subtractor designs that are used in many DSP applications. This paper proposes the efficient Adder/Subtractor design in terms of gate count, garbage outputs, constant inputs and quantum cost. The proposed circuits will simulated using ModelSim simulator and implemented on Xilinx FPGA platform.


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