Improved Meta-Flattened Butterfly Multistage Interconnection Network
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10.5120/12915-9889 |
Kawalpreet Kaur and Sandeep Sharma. Article: Improved Meta-Flattened Butterfly Multistage Interconnection Network. International Journal of Computer Applications 74(9):34-37, July 2013. Full text available. BibTeX
@article{key:article,
author = {Kawalpreet Kaur and Sandeep Sharma},
title = {Article: Improved Meta-Flattened Butterfly Multistage Interconnection Network},
journal = {International Journal of Computer Applications},
year = {2013},
volume = {74},
number = {9},
pages = {34-37},
month = {July},
note = {Full text available}
}
Abstract
Parallel processing is efficient form of information processing which means to implement high performance computing systems. A communication network that links processors and memory modules determines the efficiency of these parallel systems. To provide the required connectivity and performance at reasonable cost, an interconnection network is used. Hence, multistage interconnection networks are a good way for providing communication in these systems. This paper includes two major contributions. Firstly, it describes the flaws of existing Meta-flattened Network (MFN). Secondly, a new Fault-tolerant multistage interconnection network named as Improved Meta-Flattened Butterfly Network (IMFN) is proposed that can improve the routing problems of Meta-flattened Network. Performance of the proposed network is analyzed in terms of cost and permutation possibility. The performance comparison of the IMFN with MFN shows that the proposed network IMFN gives much better performance in terms of permutation.
References
- MahsaMoazez, FarshadSafaei and Majid Rezazadeh, "Design and Implementation of Multistage Interconnection Networks for SoC Networks," International Journal of Computer Science, Engineering and Information Technology (IJCSEIT), Vol. 2, No. 5, October 2012.
- J. Duato, S. Yalamanchili, L. M. Ni, Interconnection networks: An engineering approach, Morgan Kaufmann Publishers, 2003.
- J. Kim, W. J. Dally, D. Abts, "Adaptive routing in high radix Clos network," Proceedings of the 2006 ACM/IEEE conference on Supercomputing (SC'06), 2006.
- C. Clos, "A study of non-blocking switching networks," Bell System Tech. Journal, Vol. 32, No. 2, 1953, pp. 406-424.
- J. Kim and W. J. Dally, "Flattened butterfly: A cost-efficient topology for high-radix networks," ISCA '07 Proceedings of the 34th annual international symposium on Computer architecture, Vol. 35, Issue 2, May 2007.
- Bhuyan Laxmi N. , Yang Qing and Aggrawal P. Dharma, "Performance of MultiProcessor Interconnection Networks", Proceeings of IEEE, 1989,pp. 25-37.
- Aggarwal and P. K. Bansal, "Routing and Path Length Algorithm for Cost-effective Modified Four Tree Network", IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, 2002, pp. 293-297.
- J. H. Patel," Performance of processor-memory interconnection for Multiprocessor", IEEE, Transaction on computers, Vol. 30,No. 10,pp,771-780,1981.
- Sandeep Sharma,K. S Kahlon,P. K Basnal," Reliability and path length analysis of irregular fault tolerant multistage interconnection network", PAGE 16-23, ACM SIGARCH Computer Architecture News,2009.
- Rinkle Aggarwal and Lakhwinder Kaur,"Design and Bandwidth Analysis of Fault-Tolerant Multistage Interconnection Networks", Journal of Computer Science 4 (11): 963-966, 2008
- Sandeep Sharma, and P. K. Bansal, "A new fault tolerant Multistage Interconnection Network", IEEE TENCON'02, vol 1,2002, pp 347-350.
- H. J. Siegel, "Interconnection Network for large-Scale Parallel Processing": theory and Case studies, McGraw Hill Second Addition, 1992, pp. 1- 4,271-274.
- Sergio D'Angelo,Alderighi Monica, Fabio Casini, Salvi Davide and Giacomo R. Sechi, "A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applicaions", Proceedings of the First IEEE International Workshop ON Electronic Design, Test and Applications (DELTA. 02) IEEE,2002