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A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors

International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 77 - Number 5
Year of Publication: 2013
Manan Sethi
Karna Sharma
Paanshul Dobriyal
Navya Rajput
Geetanjali Sharma

Manan Sethi, Karna Sharma, Paanshul Dobriyal, Navya Rajput and Geetanjali Sharma. Article: A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors. International Journal of Computer Applications 77(5):30-35, September 2013. Full text available. BibTeX

	author = {Manan Sethi and Karna Sharma and Paanshul Dobriyal and Navya Rajput and Geetanjali Sharma},
	title = {Article: A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {77},
	number = {5},
	pages = {30-35},
	month = {September},
	note = {Full text available}


Among the assorted logic styles used in fostering the integrated circuits, the domino logic styles offers higher speed and smaller transistor count as compared to the static cmos circuits. However the domino logic suffers from lower noise immunity and higher power dissipation due to the problem of charge sharing and sub-threshold leakage currents. In this paper some of the earlier proposed techniques to reduce the power consumption of the domino circuits like Dual threshold voltage (DTV) and Dual threshold voltage–voltage scaling(DTVS) have been analyzed. A novel stacked transistors Dual threshold voltage (ST-DTV) approach which deploys DTV technique with stacked transistors together with a voltage regulated static keeper is analyzed to abate the total power dissipation of the circuit together with a better Power delay product (PDP). The ST-DTV design is tested on a 3-input OR gate and a 4x1 multiplexer at 90nm technology on multiple voltages and frequencies. Tanner tool EDA v13. 0 is used for simulation.


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