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Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder

by S. Baba Fariddin, E. Vargil Vijay
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 79 - Number 16
Year of Publication: 2013
Authors: S. Baba Fariddin, E. Vargil Vijay
10.5120/13943-1784

S. Baba Fariddin, E. Vargil Vijay . Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder. International Journal of Computer Applications. 79, 16 ( October 2013), 10-14. DOI=10.5120/13943-1784

@article{ 10.5120/13943-1784,
author = { S. Baba Fariddin, E. Vargil Vijay },
title = { Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder },
journal = { International Journal of Computer Applications },
issue_date = { October 2013 },
volume = { 79 },
number = { 16 },
month = { October },
year = { 2013 },
issn = { 0975-8887 },
pages = { 10-14 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume79/number16/13943-1784/ },
doi = { 10.5120/13943-1784 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:53:08.593016+05:30
%A S. Baba Fariddin
%A E. Vargil Vijay
%T Design of Efficient 16-Bit Parallel Prefix Ladner-Fischer Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 79
%N 16
%P 10-14
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A parallel-prefix adder gives the best performance in VLSI design. However, performance of Ladner-Fischer adder through black cell takes huge memory. So, gray cell can be replaced instead of black cell which gives the Efficiency in Ladner-Fischer Adder. The proposed system consists of three stages of operations they are pre-processing stage, carry generation stage, post-processing stage. The pre-processing stage focuses on propagate and generate, carry generation stage focuses on carry generation and post-processing stage focuses on final result. In ripple carry adder each bit of addition operation is waited for the previous bit addition operation. In efficient Ladner - Fischer adder, addition operation does not wait for previous bit addition operation and modification is done at gate level to improve the speed and to decreases the memory used.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Ripple carry adder Efficient Ladner–Fischer adder Black cell Gray cell