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Parallel Simulated Annealing Algorithm for Standard Cell Placement in VLSI Design

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 87 - Number 1
Year of Publication: 2014
Aaquil Bunglowala
Manisha Jain

Aaquil Bunglowala and Manisha Jain. Article: Parallel Simulated Annealing Algorithm for Standard Cell Placement in VLSI Design. International Journal of Computer Applications 87(1):23-26, February 2014. Full text available. BibTeX

	author = {Aaquil Bunglowala and Manisha Jain},
	title = {Article: Parallel Simulated Annealing Algorithm for Standard Cell Placement in VLSI Design},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {87},
	number = {1},
	pages = {23-26},
	month = {February},
	note = {Full text available}


Simulated Annealing (SA) is a stochastic based heuristic optimization technique based on physical process of metal crystallization. Optimization of Non-Deterministic polynomial hard (NP-hard) problems of non-trivial sizes is done using heuristic approach. Until now, simulated annealing (SA), genetic algorithm (GA) and Hopfield neural network (HNN) were individually used for solving the standard cell placement (SCP) problem. Simulated annealing established as a powerful SCP optimization tool, its drawback has always been its appetite for computational resources. In light of this, we are interested in the application of these parallel simulated annealing algorithms with respect to standard cell placement. Several generalized algorithms proposed for parallelizing simulated annealing, only a few have been applied to cell placement. Parallel moves has been the most popular strategy and in this paper we present a new implementation of this approach.


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