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Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 87 - Number 11
Year of Publication: 2014
Somdip Dey
Mamatha S. Nair

Somdip Dey and Mamatha S Nair. Article: Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols. International Journal of Computer Applications 87(11):6-13, February 2014. Full text available. BibTeX

	author = {Somdip Dey and Mamatha S. Nair},
	title = {Article: Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {87},
	number = {11},
	pages = {6-13},
	month = {February},
	note = {Full text available}


To improve the efficiency of a processor to work with data, cache memories are used to compensate the latency delay to access data from the main memory. But because of the installation of different caches in different processors in a shared memory architecture, makes it very difficult to maintain consistency between the cache memories of different processors. For that reason, having a cache coherency protocol is really essential in those kinds of system. There are different coherency protocols for caches to maintain consistency between different caches in a shared memory system. Few of the famous cache coherency protocols are MSI, MESI, MOSI, MOESI, MERSI, etc. In this paper, the primary focus were to study the working protocols of MESI (Modified-Exclusive-Shared-Invalid) and MOESI (Modified-Owned-Exclusive-Shared-Invalid) cache coherency protocols by designing a simple cache simulator in java, and publish the results and research findings. The main purpose of this paper is to provide new researchers and computer science students the idea regarding how to build and implement a simulator in order to understand the novel cache coherency protocols.


  • Herlihy, M. , Shavit, N. , "The Art of Multiprocessor Programming", Elsevier.
  • Hwang, K. , Xu, Z. , "Scalable Parallel Computing: Technology, Architecture, Programming". McGraw-Hill, New York, NY, 1998. ISBN 0-07-031798-4.
  • Papamarcos, M. S. , Patel, J. H. , "A low-overhead coherence solution for multiprocessors with private cache memories". Proceedings of the 11th annual international symposium on Computer architecture - ISCA '84 (1984). p. 348.
  • Neupane, M. , "Cache Coherence", California State University San Bernardino, 2004, Online. [Available at http://cse. csusb. edu/schubert/tutorials/csci610/w04/MN_Cache_Coherence. pdf] [Accessed on 07/12/2013]
  • Patterson, D. , Hennessy, J. , "Computer Organization and Design (4th ed. )". Morgan Kaufmann, 2009.
  • Nicoletta, C. , Alvarez, J. , Barkin, E. , Chai-Chin Chao, Johnson, B. R. , Lassandro, F. M. , Patel, P. , Reid, D. , Sanchez, H. , Seigel, J. , Snyder, M. , Sullivan, S. , Taylor, S. A. , Minh Vo. , (November 1999). "A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect". IEEE Journal of Solid-State Circuits 34 (11): pp. 1478–1491.
  • Hennessey J. L. , Patterson, D. A. , "Computer Architecture: A Quantitative Approach".
  • Kanter D. , "The Common System Interface: Intel's Future Interconnect". Real World Tech: 5, Online. [Accessed on 07/12/2013]
  • Bournoutian, G. , Orailoglu, A. , "Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors", Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011, pp. 89-97.
  • Dey, S. , Nath, J. , Nath, A. , "An Integrated Symmetric Key Cryptographic Method – Amalgamation of TTJSA Algorithm, Advanced Caesar Cipher Algorithm, Bit Rotation and Reversal Method: SJA Algorithm", IJMECS, vol. 4, no. 5, pp. 1-9, 2012.
  • Dey, S. , "SD-REE: A Cryptographic Method To Exclude Repetition From a Message", Proceedings of The International Conference on Informatics & Applications (ICIA 2012), Malaysia, pp. 182 – 189.
  • Dey, S. , "SD-AREE: A New Modified Caesar Cipher Cryptographic Method Along with Bit- Manipulation to Exclude Repetition from a Message to be Encrypted", Journal: Computing Research Repository - CoRR, vol. abs/1205. 4279, 2012.
  • Dey, S. , "An Image Encryption Method: SD-Advanced Image Encryption Standard: SD-AIES", International Journal of Cyber-Security and Digital Forensics (IJCSDF) 1(2), pp. 82-88.
  • Dey, S. , Nath, J. , Nath, A. , "An Advanced Combined Symmetric Key Cryptographic Method using Bit Manipulation, Bit Reversal, Modified Caesar Cipher (SD-REE), DJSA method, TTJSA method: SJA-I Algorithm". International Journal of Computer Applications46(20): 46-53, May 2012. Published by Foundation of Computer Science, New York, USA.
  • Dey, S. , "SD-EQR: A New Technique To Use QR CodesTM in Cryptography", Proceedings of "1st International Conference on Emerging Trends in Computer and Information Technology (ICETCIT 2012)", Coimbatore, India, pp. 11-21.
  • Dey, S. , "SD-EI: A Cryptographic Technique To Encrypt Images", Proceedings of "The International Conference on Cyber Security, CyberWarfare and Digital Forensic (CyberSec 2012)", held at Kuala Lumpur, Malaysia, 2012, pp. 28-32.
  • Dey, S. , "SD-AEI: An advanced encryption technique for images", 2012 IEEE Second International Conference on Digital Information Processing and Communications (ICDIPC), pp. 69-74.
  • Dey, S. , "Amalgamation of Cyclic Bit Operation in SD-EI Image Encryption Method: An Advanced Version of SD-EI Method: SD-EI Ver-2", International Journal of Cyber-Security and Digital Forensics (IJCSDF) 1(3), pp. 238-242.
  • Dey, S. , Mondal, K. , Nath, J. , Nath, A. , "Advanced Steganography Algorithm Using Randomized Intermediate QR Host Embedded With Any Encrypted Secret Message: ASA_QR Algorithm", IJMECS, vol. 4, no. 6, pp. 59-67, 2012.
  • Dey, S. , Nath, A. , "Modern Encryption Standard (MES) Version-I: An Advanced Cryptographic Method", Proceedings of IEEE 2nd World Congress on Information and Communication Technologies (WICT- 2012), pp. 242-247.
  • Magnusson, P. S. , Christensson, M. , Eskilson, J. , Forsgren, D. , Hallberg. G. , "Simics: A full system simulation platform". IEEE Computer, 35(2):50-58, Feb. 2002.
  • Nurvitadhi, E. , Chalainanont, N. , Lu, S. L. , "Characterization of L3 Cache Behavior of SPECjAppServer2002 and TPC-C. " In Proceedings of the 19th International Conference on Supercomputing (ICS), Boston, Massachusetts, 2005.
  • Uhlig. R. A. , Mudge, T. N. , "Trace-driven Memory Simulation: A Survey", In ACM Computing Surveys, Vol. 29, 1997.
  • Luk, C. K. , Cohn, R. , Muth, R. , Patil, H. , Klauser, A. , Lowney, G. , Wallace, S. , Reddi, V. J. , Hazelwood, K. , "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. " In Proceedings of Programming Language Design and Implementation (PLDI), Chicago, Illinois, 2005.